Session 5C

1:00pm - 3:05pm

ESD Design Issues

Co-Chairs

Prasun Raha, TI
Enrico Malavasi, PDF

  1:00pm

Introduction  

1:05pm

5C-1    Low-Voltage-Triggered PNP Devices for ESD Protection Design in the Mixed-Voltage I/O Interface with Over-VDD and Under-VSS Signal Levels, Ming-Dou Ker, Wei-Jen Chang, and Wen-Yu Lo

1:35pm

5C-2    Full-Chip Analysis Method of ESD Protection Network
Sachio Hayashi, Fumihiro Minami, Masaaki Yamada

5C-3    Design to Avoid the Over-Gate-Driven Effect on ESD Protection Circuits in Deep-Submicron CMOS Processes
Ming-Dou Ker and Wen-Yi Chen