Session 3B

3:30pm - 5:35pm

Interconnect: Capacitance extraction and delay calculation

Co-Chairs

Narain Arora, Cadence
Samar Saha, Silicon Storage Tech

3:30pm

Introduction

3:35pm

3B-1            A Divide-and-Conquer Algorithm for 3D Capacitance Extraction
Weiping Shi, Fangqing Yu         

4:05pm

3B-2    Interconnect Mode Conversion in High-Speed VLSI Circuits
Y. Quéré, T. Le Gouguec, P.M. Martin, F. Huret       

4:35pm

3B-3    A Comprehensive Analytical Capacitance Model of a Two Dimensional Nanodot Array Anirban Basu, Sheng-Chih Lin, Christoph Wasshuber, Adrian M. Ionescu, and Kaustav Banerjee   

5:05pm

3B-4        Efficient Capacitance Extraction for Periodic Structures by Shanks Transformation
Ye Liu, Mei Xue, Zheng-Fan Li, Rui-Feng Xue

5:20pm

3B-5    PARADE: PARAmetric Delay Evaluation under Process Variation
Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi