Tutorial Track B

Design for Manufacturing & Yield

Chair and Moderator: Duane Boning, MIT

Tutorial B1

09:00am – 10:30pm

Testing and Yield of Integrated Circuits

Organizer and Presenter: Zoran Stamenkovic, IHP GmbH

Yield is one of the cornerstones of a successful integrated circuit (IC) manufacturing technology along with product performance and cost. Many factors contribute to the achievement of high yield but also interact with product performance and cost. A fundamental understanding of yield limitations enables the up-front achievement of this technology goal through circuit and layout design, device design, materials choices and process optimization. Defect, failure and yield analyses are critical issues for the improvement of IC yield. In first part, we deal with IC fault models and test issues. Second part describes critical area models and yield models. Third part is dedicated to a local extraction approach for the extraction of IC critical areas. Finally, we present an application of above-mentioned models and extraction approach in yield forecast.

Tutorial B2

10:45am-12:15pm

Organizer: Prof. Duane Boning , MIT
Presenters: Prof. Duane Boning , MIT, Prof. Anthony Walton, University of Edinburgh, Dr. Christopher Hess, PDF Solutions

 The assessment and modeling of process variation and defectivity is becoming increasingly important in the design of high-yielding and high-performance integrated circuits. Process variation is coming from a number of sources: in addition to lot and wafer level variation, within chip variation arising from pattern dependencies is of substantial concern, affecting the matching of device and interconnect parameters. The understanding of defect sources and their impact and interaction with the layout continues to be critical to achieving required yields. The focus of this tutorial session is on test structure methodologies for yield assessment and modeling. The first segment will describe a circuit-level test structure approach, which enables the extraction and characterization of layout practice and pattern dependent effects on delay in circuits. A scan-chain approach is coupled with a large number of ring oscillator variants, so that the impact of process and layout variations on realistic circuit timing can be extracted. The second segment will describe test structures for measuring parametric characteristics such as linewidth, resistivity, contact resistance, layer thickness etc., as well as standard transistor parameters at the device level. Wafer mapping variations of these parameters with a view to identifying root causes will be briefly discussed. The section will conclude with the presentation of methods for increasing the number of devices on testchips through the use of active on-chip switching. Finally, the third segment will describe "Universal Characterization Vehicles" that combine a variety of test structures on a single chip. It covers systematic and random yield characterization like defect densities, defect size distributions and fail rates, which are important input for DFM. It also includes structures that drive SPICE modeling including statistical SPICE models for advanced analog designs. Such vehicles can evaluate the entire process flow or just a fraction of it as a short loop to decrease cycle time. This segment will cover methods for advanced area usage as well as improved test procedures that significantly reduce test time.

Tutorial B3

1:30pm-3:00pm

Design Based Yield Improvements (DBYI)

Organizer: Enrico Malavasi, PDF Solutions, Inc.
Presenters: Enrico Malavasi, PDF Solutions, Inc., Stefano Tonello, PDF Solutions, Inc.

The manufacturability of integrated circuits can be improved at design level by incorporating modifications in the structure of the IP components (cores, cells, memories) and of interconnections, as well as changes in the design methodology and flow. In this tutorial we will describe the types of design improvements that can be introduced in the design of large integrated circuits, and the potential advantages they can have for yield. These include modifications in IP cores, standard cell libraries and memory blocks, as well as interconnections. The potential impact of different techniques on the design flow will also be discussed. We will describe the technology we use to quantitatively estimate and measure yield losses due to random, systematic and parametric effects. This capability is essential to drive design modifications, in order to understand their impact, and the trade-off between conflicting requirements. 

Tutorial B4

3:15pm-4:45pm

Yield in Flash Memory: Methodology, Modeling and Design Issues

Organizer and Presenter: Giuseppe Crisenza, STMicroelectronics

In the manufacturing of Flash Memory the main defective layers are metals, vias, polysilicon and contacts. Inside a Flash Memory, most of the area is utilized for memory array with around the decoding and multiplexing circuitry. In these regions, all buses in metal and polysilicon layers are designed with the minimum layout rules admitted by technology, to match the pitch dimension of the flash cells. As the number of steps, the number of cells, and the circuit density increases, and the critical defect sizes decreases, an increasing number of defects are only seen as electrical faults. Starting from the electrical signature to the physical defect identification, a collection of various defects, typical of Flash NOR array was identified and associated with methods for electrical screening. A yield model for Flash Memories with redundancy will show the effect of the three principal factors (systematic, defect and out layer related) allowing a faster analysis of yield limiting conditions. The decomposition of yield in the described factors allows the individuation of fields where the corrective actions have to be performed and the related strategies. For defectivity yield enhancement the corrective actions are the reduction of particles or point defects: in some case a simulation methodology is proposed in order to confirming the electrical signature. For systematic yield enhancement, robustness of the circuital blocks both layout and design , and of the testing flow are the principal issues addressed.