Session EP1

Sponsored by Ammocore & Ascend Design Automation

Evening Panel Discussion

6:30pm - 8:30pm

Is Quality a Design Constraint for Sub 100nm Designs?

Organizer: Pallab Chatterjee, President and CEO, SiliconMap, LLC

Moderator: Steven Ohr, EETimes  

Description

Deep sub-micron design (below 100nm) present a number of new design challenges.  These include very high masking costs, new interconnect materials and parasitic phenomenon, significant re-engineering at the device level due to changes in basic device performance, very high gate count and pin count designs, complexity in high pin count packaging & test, and finally reduced product life in the marketplace do to the rapid rollout of new technologies.  One of the trade offs that is taking place in the industry to address these issues is the decision toward “design existence”, which is the selection of the “first functional implementation” of a design, over “design quality” which is the selection of the “optimal implementation” of a design. This panel will discuss the trends in the issue with respect to the re-targeting of the design quality issues from the SOC level to the flow and device levels and the impact on this “shift” on the manufacturability of the resulting designs.  Issues discussed will include the use of pre-tested IP as a quality metric, the coverage and quality of the EDA design and validation tools, the correlation of these metrics to the actual manufacturing process and the impact of post fabrication process steps (packaging, test, etc.) on the yield of the resulting design.

Panelists:

Callen Carpenter, President and CEO, Silicon Metrics Corp.

Dennis Monticelli, Fellow at National Semiconductor, Inc.                                             

Paul Kempf, CTO and VP Engineering, Jazz Semiconductor, Inc     

Resve Saleh, NSERC/PMC Sierra Chair, Professor, UBC Vancouver                

John Kibarian, President and CEO, PDF Solutions, Inc.      

Norm Towson, President and CEO, Netcell Corporation