Session 6A

3:30pm - 5:30pm

Interconnect Parasitic Effects

Co-Chairs

Dennis Sylvester, University of Michigan

Rajendran Panda, Motorola

3:30pm

Introduction

3:35pm

6A-1    On-Chip Interconnect Inductance - Friend or Foe (Invited), Simon Wong, Stanford University, Stanford, CA   

4:05pm

6A-2    Design and Measurement of an Inductance-Oscillator for Analyzing Inductance Impact, Takashi Sato, Hiroo Masuda1, Hitachi, Ltd., Tokyo, Japan and  1Semiconductor Technology Academic Research Center, Kanagawa, Japan

4:35pm

6A-3    On the Accuracy of Return Path Assumption for Loop Inductance Extraction for 0.1µm Technology and Beyond, SoYoung Kim, Yehia Massoud1, S. Simon Wong, Stanford University, Stanford, CA and 1Synopsys Inc., Mountain View, CA        

4:50pm

6A-4    Impact of Interconnect Pattern Density Information on a 90nm Technology ASIC Design Flow, Payman Zarkesh-Ha, S. Lakshminarayann, Ken Doniger, William Loh, Peter Wright, LSI Logic Corp., Milpitas, CA      

5:05pm

6A-5            Analyzing the Internal-Switching Induced Simultaneous Switching Noise, Li Yang, J.S. Yuan, M. Hagedorn1, University of Central Florida, Orlando, FL, 1Theseus Logic, Inc., Maitland, FL