Session 5B

1:00pm - 3:05pm

Reliability Analysis

Co-Chairs

Jayasimha Prasad, Micrel Semiconductor

Olof Tornblad, Infineon

1:00pm

Introduction     

1:05pm

5B-1            Statistical Modeling for Circuit Simulation (Invited), Colin McAndrew, Motorola, Tempe, AZ      

1:35pm

5B-2            Electrostatic Discharge Implantation to Improve Machine-Model ESD Robustness of Stacked NMOS in Mixed-Voltage I/O Interface Circuits,   Ming-Dou  Ker, Hsin-Chyh Hsu, Jeng-Jie Peng1, National Chiao-Tung University, Taiwan and 1Industrial Technology Research Institute, Taiwan

2:05pm

5B-3            Coupled Simulation of Circuit and Piezoelectric Laminates, Chenggang Xu, Terri Fiez, Kartkeya Mayaram, Oregon State University, Corvallis, OR  

2:20pm

5B-4            Investigation of the Capacitance Deviation Due to Metal-Fills and the Effective Interconnect Geometry Modeling, Won-Seok Lee, Keun-Ho Lee, Jin-Kyu Park, Tae-Kyung Kim, Young-Kwan Park, Jeong-Taek Kong, Samsung Electronics Co., Ltd., Kyunggi-do, Korea 

2:35pm

5B-5    Static Electromigration Analysis for Signal Interconnects, David Blaauw, Vladimir Zolotov1, Chanhee Oh1, Murat Becer1, Rajendran Panda1, University of Michigan, Ann Arbor, MI and 1Motorola Inc., Austin, TX