Session 3C

3:30pm - 5:30pm

Package-Design Interface Challenges

Co-Chairs

Ali Iranmanesh, Celeritek

Ken Shepard, Columbia University

3:30pm

Introduction

3:35pm

3C-1            Advanced Module Packaging Method, Peter Salmon, SysFlex, Sunnyvale, CA

4:05pm

3C-2            Electrical and Thermal Analysis for System-in-a-Package (SiP) Implementation Platform, Michael Wang, Katsuharu Suzuki, Wayne Dai, University of California, Santa Cruz, CA      

4:35pm

3C-3            Modeling and Analysis of Power Distribution Networks for Gigabit Applications, Wendem Beyene, Chuck Yuan, Joong-Ho Kim1, Madhavan Swaminathan1, Rambus, Inc. Los Altos, CA and 1Georgia Institute of Technology, Atlanta, GA     

5:05pm

3C-4    Active Device Under Bond Pad to Save I/O Layout for High-Pin-Count SOC, Ming-Dou Ker, Jeng-Jie Peng1, Hsin-Chin Jiang1, National Chiao-Tung University, Taiwan and 1ITRI, Taiwan