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Workshop III

Device and Interconnect Modeling for VDSM Era


Organizer & Moderator:

Narain D. Arora, Simplex Solutions



Technology scaling has made possible designs with millions of transistors capable of multi-GHz operations. These complex designs that results in first time silicon success requires accurate representation of the models used for the simulations and analysis of the design. The workshop provides an overview of the transistor models and the interconnects that connects these millions of devices. The workshop begins with the review of the simulation infrastructure as defined by SPICE because it has a strong influence on the development of device models. This infrastructure is relatively invariance despite the rapid changes in the fabrication technology and computer programming methodology. Moreover it gives an insight to what a good device model should be.  Model requirements in different type of simulations including DC, transient, AC, noise will be presented.  The evolution of the BSIM model from its first generation to the most recent release will be used as an example for the development of a device model.  The new modeling options currently available after years of model development and their relative tradeoff will also be presented.  Finally, a discussion on how the accelerated technology development and new software engineering paradigm may impact the traditional modeling infrastructure will be given, together with some new possibilities made available. The BSIM modeling approach is followed by surface potential based model HiSIM, Hiroshima-university STARC IGFET Model. This is the first public domain MOSFET model for circuit simulation, based on the complete drift-diffusion approximation. Since HiSIM models all advanced MOSFET phenomena closely based on their physical origins, only a small number of model parameters are required. The HiSIM2 aiming at RF applications will also be presented. The later half part of the workshop is devoted to interconnect modeling. Practical methods of accurately estimating R, C, and L of a given circuit layout that maximizes the accuracy while minimizing the time and resources that such accuracy demands will be reviewed. This is followed by other related issues as model order reduction and silicon validation of the models. Decreasing slew rates and efforts to reduce the RC delays of on-chip interconnect through design and technology have resulted in the growing importance of inductance in analyzing interconnect response for timing and noise analysis.  In the final session  we will consider recent advances in techniques to extract and analyze inductance. We will also describe characterization procedures for silicon validation of high-frequency on-chip interconnects models, including S-parameter-based frequency-domain measurements and time-domain techniques.

Workshop Schedule:

8:30-10:15 Session III-1

Circuit simulation and device modeling for new generation to come

Mansun Chan, University of California at Berkeley


10:15-10:30     coffee break


10:30-12:15 Session III-2

The 100nm-MOSFET Model HiSIM and Its Extension to RF Applications

Hiroo Masuda, M. Miura-Mattausch, STARC and University of Hiroshima, Japan 


12:15-1:15pm    lunch

1:15-3:00pm Session III-3

Challenges of VLSI interconnect modeling in the DSM era

Narain Arora, Simplex Solutions, Sunnyvale


3:00-3:15pm     coffee break

3:15-5:00pm Session III-4

A practical approach of chip level interconnect inductance extraction 

Kenneth L. Shepard, Columbia University, New York



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International Symposium on Quality of Electronic Design
Copyright 1998-2002 ISQED. All rights reserved.
Revised: February 21, 2002.