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Tutorial Track C


Interconnect and device modeling for quality design

Chair and moderator: 


Tutorial C1

08:30am 10:15am


Power/Ground Integrity Issues for Sub-130nm IC Designs


Organizer & Presenter:         

Norman Chang, Apache Design Solutions, Inc.


This tutorial introduces Power-Ground integrity, addressing its importance, verification methodology, and problem solution. Special focus will be given to inductance related L di/dt noise and LC resonance, which has been over-looked and will become significant in the near future. The impacts of these issues and methods to tame their effects will also be presented in this tutorial.



Tutorial C2

10:30am 12:15pm


A General and Comparative Study of RC(0) , RC, RCL and RCLK Modeling of Interconnects and their Impact on the Design of Multi-Giga Hertz Processors


Organizer & Presenter:         

Ersed Akcasu, OEA International, Inc.


This tutorial presents a complete step-by-step methodology for achieving the complicated task of RC(0) , RC, RCL and RCLK modeling of interconnects and their impact on the design of multi-giga hertz processors. A comparative study of interconnect model complexity is shown through simulated waveforms. Issues in clock circuit design such as shielding, why it is important and how is should be routed and tied, are explained through simulations rather than relying solely on previous practical experiences. The validation is that these methodologies and the simulations shown in this work have been instrumental in a multi-Giga Hertz processor design.



Tutorial C3

1:30pm 3:15pm


MOS Modeling, Design Quality, and Modern Analog Design


Organizer & Presenter:         Daniel Foty, Gilgamesh Associates


The first part of this tutorial will examine the present "infrastructure" of MOS modeling for circuit simulation, with particular emphasis on how history has played a role at least as large as that of engineering. The viewpoint will be that of an analog design "consumer" of MOS models who must make the best possible use of a badly flawed infrastructure. In recent years, the entire structure of MOS models has been evolving into continually more complicated and empirical forms, opening up a "reality gap" between a model's mathematical structure and circuit design usage. The need for extensive model "binning" to provide accuracy over a large range of channel geometry is causing present-day MOS models to more closely approach table-lookup methods, rather than a design-useful description of the underlying MOS technology. Among the many severe consequences of the present situation, the MOS models have become completely removed from good circuit design practices, particularly for analog design; many common analog circuits cannot even be simulated properly using "modern" MOS models! The final part of this tutorial will describe a new direction for MOS modeling, based on the use gms/Id over the range weak, moderate, and strong inversion. This approach provides a more modern grounding for understanding the MOSFET, and also leads directly into simple and powerful techniques for effective analog circuit design using modern deep-submicron technology.


Tutorial C4

3:30pm 5:15pm


RLCK Extraction and Simulation in High-Speed SoC Designs


Organizer & Presenter:         Li-Fu Chang and Keh-Jeng Chang


Signal integrity is becoming essential in today's advanced System-on-Chip (SoC) designs. According to recently published statistics for advanced VLSI/SoC design projects, more than 50% of design closure time is spent on chip verifications, especially those above 500 MHz. One key area to achieve reliable signal integrity modeling and prediction is to extract SoC's RLCK accurately and efficiently for coupling noise analysis. Innovative software architecture is needed so that PEEC method can be used in solving Maxwell equations while distributed RLCK netlists can be extracted for critical on-chip interconnects. In this tutorial, a PEEC-based SoC design software is presented. With the advent of SPICE-level full-chip simulation tools, the software must take into account the capacity of those simulators. Since the software extracts mutual inductance (K), the impact of K on signal integrity will be explained using an advanced 8-metal nanometer technology.

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International Symposium on Quality of Electronic Design
Copyright 1998 ISQED. All rights reserved.
Revised: December 25, 2001.