ieeemod.gif (2352 bytes)

csmod.gif (2025 bytes)

Session EP2


Evening Panel Discussion


Tuesday, March 19, 2002

7:00pm- 8:30pm


Process Variation: Is it too much to handle?


Organizers: Siva Narendra and Vivek De, Intel Corporation

Moderator: Ron Wilson, Editor in Chief, ISD magazine


The panel will discuss the impact of increasing process variation with technology scaling from the aspect of manufacturing, design, and design tools. Increase in process induced parameter variation makes it harder to understand the correlation between what was designed and what gets manufactured. To guarantee product quality this often results in the need for worst-case assumptions during design phase. Can we continue this? If not, should the manufacturing and process engineers get their act together and reduce variation? Or, should the circuit designers stop complaining and learn to live with the variation by building process tolerant circuits? How should the CAD community help in these endeavors?



Duane Boning, Associate Professor and Associate Director of Microsystems Technology Labs, MIT, Cambridge, MA

Steve Duvall, Fellow and Director of Strategic Investments, Intel Corporation, Sydney, Australia

James Meindl, Professor and Director of Microelectronics Research Center, Georgia Tech, Atlanta, GA

Sani Nassif, Manager, IBM Austin Research Lab, Austin, TX

Jan Rabaey, Professor and Co-founder Berkeley Wireless Research Council, University of California Berkeley, CA

Doug Verret, Fellow and Director of Yield, Texas Instruments, Austin, TX



Home| Conference| Committee| Sponsors| Resources| Registration| News

International Symposium on Quality of Electronic Design
Copyright 1998-2002 ISQED. All rights reserved.
Revised: December 25, 2001.