Session 3A

1:00pm-3:10pm

Design Issues for Power and Noise Management

Co-Chairs: 

Ajith Amerasekera, Texas Instruments

Farid Najm, University of Toronto, Canada

1:05pm

3A-1

Device Physics Impact on Low Power, High Speed DSP Design Techniques (Invited), David Scott, Shaoping Tang, Song Zhao, and Mahalingam Nandakumar, Texas Instruments, Dallas, TX

1:30pm

3A-2

Power Supply Noise Suppression via Clock Skew Scheduling, Wai-Ching Lam, Cheng-Kok Koh and Chung-Wen Tsao¹, Purdue University, West Lafayette, IN and ¹Celestry Design Technologies, Inc., San Jose, CA

1:55pm

3A-3

Trading off Reliability and Power-Consumption in Ultra-Low Power Systems, Atul Maheshwari, Wayne Burleson and Russell Tessier, University of Massachusetts, Amherst, MA

2:20pm

3A-4

Asynchronous Circuits: An Increasingly Practical Alternative (Invited), Peter Beerel, University of Southern California, Los Angeles, CA

2:45pm

3A-5

Trends in Low Power Digital Systems on Chip Design (Invited), G. Lim and R. Saleh, University of British Columbia, Vancouver, BC, Canada