Session 1C

Design for Test

Co-Chairs: 

Jayashree Saxena, Texas Instruments

1:05pm

1C.1

Test Generation and Fault Modeling for Stress Testing (Invited), Robert C. Aitken, Agilent Technologies

1:30pm

1C.2

Extending the Viability of I_DDQ Testing in the Deep Submicron Era, Y. Tsiatouhas, Th. Haniotakis¹, D. Nikolos², and A. Arapoyanni³, Integrated Systems Development S.A., Athens, Greece, ¹Southern Illinois University, Carbondale, IL, ²University of Patras, Patras, Greece, and ³University of Athens, Athens, Greece

1:55pm

1C.3

Design of Reconfigurable Access Wrappers for Embedded Core Based SOC Test, Sandeep Koranne, Philips Research Laboratories, Endhoven, The Netherlands

2:20pm

1C.4

Testing of Analogue Circuits via (Standard) Digital Gates, Daniela De Venuto, Michael J. Ohletz¹ and Bruno Ricco², Politecnico di Bari, Bari, Italy, ¹Alcatel Microelectronics, Zaventem, Belgium and ²Universita di Bologna, Bologna, Italy

2:45pm

1C.5

Automatic Test Program Generation from RT-Level Microprocessor Descriptions, F. Corno, G. Cumani, M. Sonza Reorda, and G. Squillero, Politecnico di Torino, Torino, Italy