IEEE ISQED 2000 TUTORIALS
The ISQED 2000 tutorials include 15 tutorials, organized in three tracks. Allowing time, participants can attend any of the desired tutorials. All participants would receive a copy of the tutorial book, which contains all tutorials. These tutorials are as follows:
TUTORIAL TRACK I
DESIGN FOR RELIABILITY & MANUFACTURABILITY
Organizer & Moderator: Prof. Ibrahim Hajj
University of Illinois at Urbana-Champaign
MOS Models as a Factor in the Quality of Electronic Design
Organizer: Daniel Foty, Gilgamesh Associates
Presenter: Daniel Foty, Gilgamesh Associates
The objective of this tutorial is to acquaint the circuit designer with the various problems and pitfalls inherent in the MOS modeling "infrastructure." The tutorial will provide a top-to-bottom overview of how MOS models and MOS modeling affect the quality of integrated circuit design. MOS modeling will be separated into a hierarchy of semiconductor physics, mathematical interpretations, circuit simulator implementations, and parameter determination. A variety of problems at each of these levels reduces the effectiveness of the MOS model description in the circuit design environment. Many of these problems can be "worked around" by the well-informed circuit designer, while others will require fundamental changes to how MOS modeling is approached.
Design-in Hot Carrier Reliability Modeling and Simulation
Organizer: Chune-Sin Yeh, BTA Technology
Presenter1: Bruce McGaughy, BTA Technology
Presenter 2: Hirokazu Yonezawa, Matsushita Electric Industrial
The tutorial addresses the hot carrier reliability modeling of devices and the design challenges associated with that, and provides a summary of solutions to these challenges. At the end of the tutorial participants should be able to understand the hot carrier effect and its impact on circuits, as well as the growing needs and benefits of EDA-assisted design for reliability. Participants will also be exposed to an innovative design flow which enables virtual qualification testing early in the design cycle before manufacturing.
Thermal Effects in Deep Submicron VLSI Interconnects
Organizer: Kaustav Banerjee, Stanford University
Presenter: Kaustav Banerjee, Stanford University
Thermal effects are an inseparable aspect of electrical power distribution and signal transmission through the interconnects in VLSI circuits due to self-heating caused by the flow of current. They impact interconnect design and electromigration reliability. For deep-submicron technologies, thermal effects are increasing due to aggressive interconnect scaling and introduction of new dielectric materials with poor thermal properties. Furthermore, thermally accelerated failures in deep-submicron VLSI interconnects under high-current stress conditions, such as electrostatic discharge (ESD), have become a reliability concern. This tutorial will begin with an introduction to the fundamentals of modeling thermal effects under a wide range of current conditions in advanced interconnect structures. Interconnect scaling trends and their implications for interconnect performance, thermal effects, and reliability will be analyzed simultaneously. Self-consistent interconnect design approach, which comprehends both electromigration and self-heating, will be discussed, and quantitative analysis of reliability and performance of low-k/Cu interconnect systems will be presented. Additionally, interconnect design for high-current (ESD) robustness will also be examined.
Design with Copper & the Reliability Impact
Organizer: David Overhauser, Simplex
Presenter 1: James Lloyd, Jet Propulsion Lab
Presenter 2: Ted Williams, MorphICs
Copper metalization in ICs has been in research for decades. Now that copper is available to replace aluminum wires it is important to understand the reliability tradeoffs of copper with respect to aluminum. This tutorial contains two topics addressing this issue. The first presents the metal reliability of copper as compared to modern aluminum. The tradeoffs designers make are presented. The second topic presents the analysis and design process designers require to create quality designs with copper metalization. Typical examples are used to illustrate this analysis for signal and power wire reliability.
Physical Design of Mixed-Signal VLSI Chips
Organizer: Tuna B Tarim, Ohio State University
Presenter 1: Mohammed Ismail, Ohio State University
Presenter 2: Tuna B Tarim, Ohio State University
Presenter 3: Georges G.E. Gielen, Katholieke Universiteit Leuven, Leuven,Belgium
To produce cost-effective, manufacturable analog and mixed-signal chips, circuit designers must work to enhance functional yield. This is even more critical for sub-micron low voltage designs since random variations do not scale down with feature size or supply voltage. Moreover, with current trends of higher levels of integration leading to complete mixed-signal systems on a chip, yield loss due to the analog part must be minimized such that it has little effect on the yield of the mixed-signal chip. This tutorial deals with basic principles of statistical modeling, simulation, design and optimization techniques for yield enhancement of analog ICs at both circuit and layout levels. The material will be given at an introductory level. Students and new comers are encouraged to attend. The tutorial delivers description of statistical modeling, simulation, design and optimization techniques for yield enhancement of analog ICs at both circuit and layout levels, and of automated analog layout generation for performance and quality.
TUTORIAL TRACK II
DESIGN FOR RELIABILITY & MANUFACTURABILITY
Organizer & Moderator: Dr. Ali Iramanesh, Synopsys Inc.
Quality Library Design
Organizer: Mostafa Torkian, Sycon Design
Presenter: Jack Feldman, Sycon Design
With the increase in circuit speed and technology shrink cell layout generation poses more challenges in the IC design process. This tutorial will focus on cell layout aspects in light of current technologies, circuit design styles, methodologies and flows. It is intended for circuit and layout designers, for CAD engineers, and for academic researchers.
The first part will review layout problems and quality measures for both standard cells and custom cells. Examples of various layout architectures illustrate layout design trends and problem complexity. Problem formulations and latest solution techniques will be summarized. The second part will review flows and methodologies. We will motivate the need for "on the fly cell generation" methodology. An outlook for emerging methodologies, tools, state-of-the art techniques will conclude the tutorial.
Voltage Drop Effects on DSM VLSI Design
Organizer: Tak K. Young, Synopsys
Presenter: Tak K. Young, Synopsys
Voltage drop effect is important for deep sub-micron designs. With large currents through the power and ground of a circuit, there can be significant voltage difference at the transistor connections from the supply values. This tutorial will address how this effect will influence the performance of the circuit. A method to identify the problem areas will be described. The need for the appropriate input vectors will be discussed together with a method to generate the input vectors. A graphical-user-interface will then be presented to provide the environment to identify the solution to the voltage drop problem. For very large designs, a hierarchical model is described to model each of the blocks for the complete circuit.
Signal and Power/Ground Integrity for IC and Package
Organizer: Shen Lin, Hewlett-Packard Labs
Presenter 1: Shen Lin, Hewlett-Packard Labs
Presenter 2: Jiayuan Fang, UC Santa Cruz
With the advance of semiconductor manufacturing, EDA, and VLSI design technologies, circuits with increasingly higher speed are integrated into increasingly higher density. It has been well recognized and projected that serious challenges for the design of future high-speed circuits are the signal integrity with the consideration of on-chip inductance effects and the power and ground distribution systems from chip to package and their interactions with signal distribution systems. This tutorial is composed of two topics: (1) on-chip inductance and inductive coupling, and (2) power, ground, and signal integrity analysis of IC packages and printed circuit boards. Issues such as on-chip inductance calculation, return path determination, skin- and proximity-effects, and methods to control inductance will be introduced for the first topic. Electrical characteristics covered in the second topic include coupling between traces and vias, power and ground voltage fluctuations, decoupling capacitor placement, electromagnetic resonance and radiation. Electrical characterization of signal, power and ground distribution systems of packages will be illustrated. Numerical techniques and tools for the power, ground and signal integrity analysis in IC packages and printed circuit boards will be reviewed.
Accurate Analysis of Cross-Talk Effects In DSM Designs
Organizer: Hemendra Godbole, Synopsys
Presenter 1: Ken Shepard, Cadmos
Presenter 2: Peivand Tehrani, Synopsys
With the continuing advance of CMOS scaling, noise and signal integrity issues have become an important concern in the design of digital integrated circuits. We consider two effects of noise in deep submicron design: functional failures and delay modification. Functional failures are addressed by a new class of static noise analysis tools. Delay effects are considered with enhancements to static timing analysis. After a brief overview of the noise issues plaguing deep submicron digital integrated circuits, we consider the design and analysis issues associated with noise.
In the first part of the tutorial, we focus on functional failures due to signal integrity issues. Static noise analysis as a means of validating the noise immunity of circuits through the design process is considered. We also consider good design practices for managing noise. In the second part of the tutorial, we consider the effect of noise on delay and how this influences timing closure for custom and SoC designs. Including crosstalk effects within static timing analysis is considered. Finally, a design methodology including both static timing and noise analysis is considered, along with the required synergy between these two analysis engines.
Managing Noise in VDSM Designs
Organizer: Shashank Goel, Sapphire Design
Presenter 1: Steven McCormick, Sapphire Design
Presenter 2: Sudhakar Muddu, SGI
The issue of signal integrity can no longer be overlooked with designs targeted for emerging Very Deep Sub-micron (VDSM) technologies. Many issues must be managed by design tools and methodologies to achieve successful outcomes. In this tutorial we explore the sources of noise and other signal integrity problems, methods of immunizing designs against these problems, and how the problems can be treated in VDSM ASIC design flows. The important topic of noise and crosstalk modeling standards in the ASIC design environment will also be discussed.
TUTORIAL TRACK III
CLOSING THE MANUFACTURING LOOP
Organizer & Moderator: Prof. Andrzej Strojwas
Carnegie Mellon University
Factors and Tools for Quality Physical Layout Design
Organizer: Dan Clein, PMC-Sierra Inc, Ottawa Design Center, CANADA
Presenter 1: Dan Clein, PMC-Sierra Inc, Ottawa Design Center, CANADA
Presenter 2: Gregg Shimokura, ST Microelectronics, Ottawa Design Center, Canada
The basic question in physical design is "what are quality metrics" for it. Making a decision about flows and tools to meet client requirements is not such an easy job without proper training. Another problem each designer has to face is that tool vendors are trying to convince us that each new tool is "obligatory" if we want to achieve project goals. Understanding the features and limitations of each class of tool will enable the user to decide if the conditions of the current flow and/or the tools need to be improved to adapt to new "requirements". In this tutorial, the authors of "CMOS IC Layout Concepts, Methodologies and Tools ", will define the conditions for quality physical layout design, explain
a few layout concepts and methodologies, layout tool trade-offs versus flows, and will introduce tools used for IC layout design with their capabilities and limitations.
SubWavelength Design: Lithography Effects and Corrections
Organizer: Susan Lippincott, Numerical Technologies
Presenter 1: Yao-Ting Wang, Numerical Technologies
Presenter 2: Andrew Kahng, UCLA
For several years the key obstacles for the EDA and IC communities have been the "system-on-chip challenge" and the "deep submicron challenge". These two challenges emerged as IC feature sizes shrank and IC complexity exploded, spawning a new set of design solutions. Today, as the industry introduces the 0.18 micron process generation, a new and larger challenge emerges: the Subwavelength Challenge, where IC feature sizes become smaller than the wavelength of light used to produce them. This ‘Subwavelength Challenge’ will exist beyond the 0.18 micron generation, throughout the life of optical lithography.
The implications of the subwavelength challenge reach across the IC design to manufacturing spectrum, demanding new technologies, such as phase-shifting and OPC, to address them. The introduction of these technologies fundamentally changes the relationship between design and manufacturing, and how physical effects can be abstracted from silicon. In order to maintain quality in the design process, these effects must be considered. This tutorial will introduce two subwavelength technologies: OPC and phase-shifting, and will discuss the changes needed to the design flow in order to incorporate them.
How to use Layout Compaction Technology to Solve Timing, Power, and Signal integrity Problems in UDSM Technology
Organizer: Gabriele Eckert, Rubicad
Presenter 1: Michael Reinhardt, Rubicad
Presenter 2: Illam Pakkirisamy, Qualcomm
With the advent of ultra deep sub-micron technologies IC designers face timing and signal integrity problems on the layout level which cannot be seen in the high-level description.
But what if the physical mask layout does not meet the specification? No matter which design flow they have installed, IC designers need a flexible layout correction approach so they can automatically adjust the mask layout to the target requirements for timing and for signal integrity problems such as crosstalk.
This tutorial discusses various solutions to solve timing and signal integrity problems on the physical layout level. It introduces automatic methods to solve these problems with the emphasis on design migration and compaction technology.
Physical Verification at 0.25 micron and Below
Organizer: Pat LaCour, Mentor Graphics
Presenter: Andrew Moore, TSMC
The advent of 0.25-micron production processes has increased capacity to multi-million gate designs. The data that must be managed is measured in hundreds of MB and billions of polygons. In addition, physical aspects of manufacturing must now be dealt with at the design stage, going far beyond traditional DRC.
The tutorial will present a survey of hierarchical verification and manufacturing issues that are required today and in the future. Example solutions of common problems in the field today will be shown, including CMP density and tiling, antenna detection, and SOC verification.
Implementation Issues for Production RET (OPC and PSM)
Organizer and Presenter: Pat LaCour, Mentor Graphics
As semiconductor processes continue to shrink, we are increasingly in the photolithography region where the geometry patterned is smaller than the wavelength of the light used to pattern it. Several optical techniques that enable this are commercially available today. This tutorial will discuss the practical implications of these techniques and outline requirements for integration of these optical corrections into a production design environment. The challenges include run-time performance, output data expansion, and post-correction verification.
The tutorial will discuss all aspects currently being encountered by users in deploying these optical techniques. Examples of statistics, problems, and production flows will be included.