Co-Chairs: Glendy Sun, TSMC, Vinod Malhotra, Numerical Technologies

3:25pm

Introduction

3:30pm

5B.1 Design And Variability, Or Why We Need To Get Closer To The Edge (Invited)

Sani R. Nassif, IBM Austin Research Laboratory, Austin, TX

3:55pm

5B.2 Realistic Worst-Case Modeling by Performance Level Principal Component Analysis

Alessandra Nardi*, Andrea Neviani*, Carlo Guardiani**, *DEI, Universita‘ di Padova, Padova, Italy, **PDF Solutions, Inc. San Jose, CA

4:20pm

5B.3 Efficient Full-Chip Yield Analysis Methodology for OPC-Corrected VLSI Designs

V. Axelrad*, N. Cobb**, M. O’Brien**, V. Boksha***, T. Do**, T. Donnelly**, Y. Granik**, E.Sahouria**, A. Balasinski****, *SEQUOIA Design Systems, Woodside, CA, **Mentor Graphics, San Jose, CA, ***MIT Sloan School of Management, Cambridge, MA, ****Cypress Semiconductor, San Jose, CA

4:45pm

5B.4 Electronic Process Limited Yield

Gary W. Maier*, Shawn Smith**, *IBM, ** Knights

5:10pm

5B.5 Effects of Package Stackups on Microprocessor Performance

Mehdi Mechaik, Cisco Systems, San Jose, CA