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Session 3C

Wednesday 3/22/00

10:40am - 12pm


Poster Session


Co-Chairs: Norman Chang, Hewlett Packard, C.K. Cheng, University of California, San Diego




3C.1 Power Bus Maximum Voltage Drop in Digital VLSI Circuit

G. Bai, S. Bobba and I. N. Hajj, University of Illinois at Urbana-Champaign, IL

3C.2 A Reliable Clock Tree Design Methodology for ASIC Designs

Mely Chen Chi*, and Shih-Hsu Huang**, *Chung Yuan Christian University, Chung Li, Taiwan, **Industrial Technology Research Institutes, Hsinchu,Taiwan

3C.3 Fixing Antenna Problem by Dynamic Diode Dropping and Jumper Insertion

Peter H. Chen, CS Ying, Geoffrey Ying, and CM Peng, Tera Logic, Inc. Mountain View, CA

3C.4 Managing Multi-Chip Module (MCM) Projects

Donald J. Dent, University of Luton, UK

3C.5 A Layout Approach for Electrical and Physical Design Integration of High-Performance Analog Circuits

Mohamed Dessouky and Marie-Minerve Louerat, Universit´e Pierre et Marie Curie, Paris, France.

3C.6 On Testability Of Multiple Precharged Domino Logic

Th. Haniotakis*, Y Tsiatouhas*, D Nikolos** and C Efstathiou*** , *ISD S.A Athens, Greece, **University of Patras, Patras, Greece, ***TEI of Athens, Athens, Greece

3C.7 Dvdt: Design For Voltage Drop Test Using On-chip Voltage Scan Path

Makoto Ikeda, Hideyuki Aoki and Kunihiro Asada, University of Tokyo, Tokyo, Japan

3C.8 EMI Common-Mode Current Dependence on Delay Skew Imbalance in High Speed Differential Transmission Lines Operating at 1 Gigabit/second Data Rates

J.L. Knighten*, L.O. Hoeft**, J.T. DiBene II***, and N.W. Smith*, *NCR Corporation, San Diego, CA, **Consultant, Albuquerque, NM, ***Convergence Design, San Diego, CA

3C.9 Internet-based Virtual Manufacturing: a VerificationTool for IC Designs

Wieslaw Kuzmicz, Warsaw University of Technology, Warszawa, Poland

3C.10 A Reconfigurable Low-power High performance Matrix Multipler Design

Rong Lin, SUNY- Geneseo, Geneseo, NY

3C.11 Electrical Characterization of Signal Routability and


Mehdi Mechaik, Cisco Systems, San Jose, CA

3C.12 Full-Chip Signal Interconnect Analysis for Electromigration Reliability

Steffen Rochel* and NS Nagaraj**, *Simplex Solutions, Sunnyvale, CA, **Texas Instruments, Dallas, TX

3C.13 Correct-by-Design CAD Enhancement for EMI Signal Integrity

E McShane and K. Shenai, University of Illinois at Chicago, Chicago, IL

3C.14 A Transition Based Mixed-Signal BIST Approach

Alvernon Walker* and Parag K Lala**, *University of Tennessee, Knoxville, TN, **University of South Florida, Tampa, FL

3C.15 Aliasing-free Space and Time Compaction with Limited Overhead

Jin Ding, Xiaojun Wang, and Charles McCorkell, University, Dublin , Ireland

3C.16 A Pre-Simulation Measure of d.c. Design-for-Testability Fault Diagnosis Quality

Matthew Worsman, Mike W. T. Wong, and Y. S. Lee, The Hong Kong Polytechnic University, Hung Hom, Kowloon, Hong Kong

3C.17 An Automated Shielding Algorithm and Tool for Dynamic Circuits

Gin Yee*,**, Ron Christopherson*, Tyler Thorp*, Ban Wang* , and Carl Sechen**, *Sun Microsystems, Sunnyvale, CA, **University of Washington, Seattle, WA

3C.18 Deriving Dominant Harmonic Frequencies for Accurate VLSI Interconnect Impedance Extraction

Li-Fu Chang, Keh-Jeng Chang, Christophe Bianchi, FrequencyTechnology, Santa Clara, CA

3C.19 Applying the OpenMORE Assessment Program for IP Cores

Jean-Pierre Guéguen*, Pierre Bricaud**, *Synopsys, Mountain View, CA, **Mentor Graphics, San Jose, CA

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International Symposium on Quality of Electronic Design
Copyright © 1998 ISQED. All rights reserved.
Revised: May 13, 2001 .