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Session 2C

Tuesday 3/21/00

3:25pm - 5:35pm


Low Power Test


Co-Chairs:    Marcel Jacomet, Berner FH, HTA Biel, Ibrahim Hajj, University of Illinois at Urbana- Champaign





2C.1 Design for Testability in Nanometer Technologies:

Searching for Quality (Invited)

T.W. Williams, and Rohit Kapur, Synopsys, Mountain View, CA


2C.2 Low Power Testing of VLSI Circuits: Problems and Solutions (Invited)

Patrick Girard, LIRMM, Montpellier, France


2C.3 On Effective IDDQ Testing of Low Voltage CMOS Circuits Using Leakage Control Techniques

Zhanping Chen, Liqiong Wei and Kaushik Roy, Purdue University, IN


2C.4 Efficient Hierarchical Approach to Test Generation for

Digital Systems

Raimund Ubar, and Jaan Raik, Tallinn Technical University, Tallinn, ESTONIA


2C.5 Quality of Electronic Design: from Architectural Level

to Test Coverage

O.P. Dias*, J. Semião**, M.B. Santos***, I.M.Teixeira***, and J.P. Teixeira***, *Escola Superior de Tecnologia Instituto Politécnico de Setúbal, INESC, Portugal, **Escola Superior de Tecnologia Universidade do Algarve, INESC, Portugal, ***Instituto Superior Técnico Universidade Técnica de Lisboa, INESC, Portugal

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International Symposium on Quality of Electronic Design
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Revised: May 13, 2001 .