Session 2B

3:25pm

Introduction

3:30pm

2B.1 LEMINGS: LSI's EMI-Noise Analysis with Gate Level Simulator

Kenji Shimazaki, Hiroyuki Tsujikawa, Seijiro Kojima, and Shouzou Hirano, Matsushita Electric Industrial, Kyoto, Japan

3:55pm

2B.2 Dynamic Timing Analysis Considering Power Supply Noise Effects

Yi-Min Jiang*, Angela Krstic** and Kwang-Ting (Tim) Cheng**, *Synopsys Inc., Mountain View, CA, **University of California, Santa Barbara, CA

4:20pm

2B.3 Full Chip Thermal Simulation

Zhiping Yu*, Dan Yergeau*, Robert Dutton*, Sam Nakagawa**, Norman Chang**, Shen Lin**, Weize Xie**, *Stanford University, CA, ** HP, Palo Alto, CA

4:45pm

2B.4 Enabling Dir(designing-in-reliability) Through CAD Capabilities (Invited)

Wonjae K Kang*, Brad Potts**, Ray Hokinson***, John Riley#, David Doman##, Frnak Cano###, N.S. Nagaraj###, Noel Durrant$, *Intel, Santa Clara, CA, **AMD, *** Compaq, #Lucent Technologies, ##Motorola, ###Texas Instruments, $Sematech

5:10pm

2B.5 Noise Safety Design Methodologies

M Graziano, M Delaurenti, G Masera, G Piccinini, M Ruo Roch, M Zamboni, Politecnico di Torino, Torino, Italy