The 1^st IEEE International Symposium on Quality Electronic Design, ISQED 2000, was successfully held on March 20 through March 22, in DoubleTree hotel, San Jose, CA. The conference drew more than 300 attendees from Design, EDA, and Semiconductor disciplines, well exceeding expectations of the organizing committee. This is the first occurrence of this truly multi-disciplinary and international conference devoted to the critical issue of quality design. About 20 countries were represented in the conference, through papers, panels, and tutorials, spanning more than 200 organizations worldwide. A great collection of papers from IC design, EDA, test, equipment, universities, and foundries, marked a tremendous start for the conference. The symposium audience, were designers of the integrated circuits and system, those involved with the design and application of EDA tools and methodologies, process technologists and manufacturing specialists. ISQED was sponsored by the IEEE computer society, technical committees on VLSI and Design Automation, and was held in cooperation with FSA, and IEEE TTTC. The conference was made possible through financial contribution and support from EE Times, Fujitsu Microelectronics, Intel, Monterey Design, Numerical Technologies, Sun Microsystems, Sycon Design, Synopsys, and UMC group (USA).

Plenary Sessions

ISQED realizes that achieving design quality requires close work between all disciplines involved in the design process. This was reflected in two plenary session which were held on Tuesday morning and Wednesday morning. Seven industry and academia leaders delivered keynote speeches, addressing the design quality and the issues surrounding that, from their point of view and the point of view of the disciplines they represent.

In his opening remarks, Dr. Ali Iranmanesh, the ISQED founder and chair, described the conference vision and goals, and the critical need for cooperation between design, EDA, and semiconductor communities for achieving the design quality. He then called upon the industry to develop a unified master roadmap for design tools and capabilities enabling designers to design chips, matching the complexity levels outlined in SIA's ITRS, in a time frame dictated by the time to market constraints. "Design tools and methodologies should enable designers to create circuits working and yielding the first time, and lasting over the specified product life" he noted further. Then the first keynote speech, Dr. Aart de Geus, Chairman and CEO of Synopsys, explored the various trade-off involved in the design process and presents the EDA view of the design quality. In the second keynote, John East, President and CEO of Actel offered his practical definition of quality. He further proposed a process for achieving the design quality and time to market. After that, Sudhir Chandratreya (covering for Prakash Agrawal, President and CEO of NeoMagic), presented the process needed to design a quality chip for manufacturing and explains the milestones necessary for bringing a successful chip to market. Dr. John Kibarian, President and CEO of PDF Solutions concluded the first plenary session with his speech. Kibarian outlined the key technical issues, which make performance and yield targets difficult to meet given the product’s life-style constraints, and demonstrated how these new methodologies can greatly change the production ramp. The second plenary session was held on Wednesday morning and was chaired by Dr. Resve Saleh, the ISQED plenary chair. The first speaker, professor Alberto Sangiovanni-Vincentelli of Berkeley, explored methods for selecting families of software and hardware architectures that would allow a substantial design re-use and some paradigms for embedded system designs. Dr. Yervant Zorian, Chief Technology Advisor of LogicVision, then presented various design for quality trends and solutions and will analyze their impact on test, as well as a set of expanded quality insurance functions to support debug, measurement, diagnosis and repair. Professor Kamran Eshraghian of Edith Cowan University gave the third keynote speech. In this keynote speech, Dr. Eshraghian explored design paradigm changes required to cope with the design and quality of the new system complexity. In future the video tape and presentation slides of all the plenary speakers will be made available through the conference web site at http://www.isqed.org.

ISQED Panels

Five panel discussions with close to 30 top specialists pondered on key topics including "Quality EDA Tool flows," "Quantifying Quality in Electronic Design," and "The Hidden Costs of Design Quality". ISQED panel discussions were well received by the audience. The first panel discussion titled "How Do You Select A High Quality EDA Tool Flow?" was sponsored by UMC, organized by Robert Blair of BNR International, and moderated by Jacques Benkoski of Monterey Design Systems. The panelists list included Mike Dini of the Dini Group, Dan Lincoln of ASIC International, Jim Lipman of Tech On Line, Nancy Nettleton of Sun Microsystems, Edward Wan of UMC Group (USA), and Ghassan Yacoub of Intel Corporation. The panel explored one of the critical issues facing the design community, which is how to select a high quality EDA design tool flow, and what should EDA tool providers do to close the gap with Moore's Law? The second panel discussion was organized by Michael Reinhardt of RubiCad, and moderated by Michael Santarini of EETimes. This panel was titled " What is Design Quality? How can Quality in Electronic Design be quantified?". Panel participants were; Ray Abrishami of Fujitsu Microelectronics, Heinz Holzapfel of Infineon, Mike Keating of Synopsys, Bill Price of Philips Semiconductors, Krishna of University of Illinois at Chicago, Greg Spirakis of Intel, and Noel Strader of Avant!. The third panel and dinner was sponsored by EE Times and titled "The hidden costs of quality". Panel organizers and moderators were Richard Goering, and Richard Wallace of EE Times. Panelists were John East of Actel, Jim Ballingall of UMC, Hugh Duffy of Failure Analysis, Keith Lobo of Quickturn Design Systems, Howard Sachs of VSIA, and Gadi Singer of Intel Microprocessor Products Group. This high-level panel explored the important – but often overlooked – global, social and economic implications of design quality. It further probed the costs, to both end users and manufacturers, of poor quality. The fourth panel was titled " Focus on quality of design: Does it help or hinder time to market?". Panel organizer was Nader Vasseghi of Sebring Networks. Rita Glover of EDA moderated this panel today. Panelists included Tom Aldridge of Intel, Bulent Celebi of Scenix Semiconductor, Aurangzeb Khan of Altius Solutions, Chris Rowen of Tensilica, Ian MacKintosh of Mentor Graphics, and George Swan of Synopsys. The fifth and final panel was organized by Carlo Guardiani of PDF solutions, and moderated by Andrzej Strojwas of Carnegie Mellon University. The panel was titled "Design-Manufacturing Interface in the Deep Submicron: Is technology independent design dead?". The list of panelists included John Kibarian, of PDF Solutions, Resve Saleh of Simplex Solutions, James Spoto of Conexant, Mark Templeton of Artisan Components, and Pin-Nan Tseng of TSMC North America.

Technical Papers and Awards

A great collection of more than 60 papers from IC design, EDA, test, equipment, universities, and semiconductor were presented in twelve sessions. In Tuesday luncheon session sponsored by Synopsys, ISQED best paper award committee honored three papers from different disciplines. Zhanping Chen, Liqiong Wei, and Kaushik Roy of Purdue University received the award for their paper entitled "On Effective IDDQ Testing of Low Voltage CMOS Circuits Using Leakage Control Techniques." The second award went to Tomas Bautista and Antonio Nunez from the University of Las Palmas de Bran Canaria, Canary Islands, Spain. They authored "Synthesis Experiments and Performance Metrics for Evaluating the Quality of IP Blocks and Megacells." Finally, Shen Lin, Norman Chang, and Sam Nakagawa of Hewlett-Packard in Palo Alto, CA, received the third award for their paper entitled, "Quick On-chip Self- and Mutual-Inductance Screen." Dr. Tak Young, the ISQED technical committee chair, presented the authors with a plaque and a check for $600 to be shared among the authors of each paper. Synopsys, Sycon Design, and ISD Magazine were among the organizations sponsoring the best paper award event. The Best Paper Award committee reviewed all entries and narrowed the field down to eight finalist papers; then, the three winners were selected from this group. The award ceremony commenced during lunch and was followed by a presentation from Robert Landy of LSI Logic, who talked about incorporating the third party EDA tools into LSI's design flow.

ISQED Tutorials

ISQED tutorial day included three parallel tutorial tracks, consisting of a total of 15 tutorials, delivered by 23 industry and academia experts. List of topics includes a wide variety of issues and methods regarding the design and quality. The first tutorial track was titled "Design for Reliability & Manufacturability". In this track, five tutorials were delivered, focusing on fundamental components of design quality. Some of the topics explored are, the quality of MOS models, Hot-Carrier effects, thermal effects, electromigration and the role of copper interconnect, statistical modeling, design and yield optimization. The second tutorial track was titled "Design for Quality" and addressed some of the key considerations and factors for a quality design. There were five tutorials presented in this track. List of topics included the quality of libraries, voltage drop effects, signal and power integrity, cross talk, and noise in VDSM designs. The third tutorial track was titled "Closing the Manufacturing Loop". As evident from the title, the focus of this track was on issues fundamental to Manufacturability. There were also five tutorials given in this track. List of topics includes factors and trends for quality physical design, deep submicron lithography effects and methods for dealing with them, layout compaction technology, and physical verification methods. The complete list of all tutorials was as follows:

• Design with Copper & the Reliability Impact
• Factors and Tools for Quality Physical Layout Design
• Quality Library Design
• Physical Design of Mixed-Signal VLSI Chips
• Physical Verification at 0.25 micron and Below
• Managing Noise in VDSM Designs
• How to use Layout Compaction Technology to Solve Timing, Power, and
• Signal integrity Problems in UDSM Technology
• Voltage Drop Effects on DSM VLSI Design
• Signal and Power/Ground Integrity for IC and Package
• Accurate Analysis of Cross-Talk Effects In DSM Designs
• MOS Models as a Factor in the Quality of Electronic Design
• SubWavelength Design: Lithography Effects and Corrections
• Implementation Issues for Production RET (OPC and PSM)
• Design-in Hot Carrier Reliability Modeling and Simulation
• Thermal Effects in Deep Submicron VLSI Interconnects

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