International Symposium on Quality Electronic Design (ISQED)

ISQED Best Papers

ISQED Best papers as well as all other ISQED papers are available from IEEE Xplore.

ISQED 2016

Reliability and Energy-aware Cache Reconfiguration for Embedded Systems

Yuanwen Huang and Prabhat Mishra
University of Florida


Digital IP Protection Using Threshold Voltage Control

Joseph Davis, Niranjan Kulkarni, Jinghua Yang, Aykut Dengi, Sarma Vrudhula
Arizona State University


ISQED 2015

A Low-Power Field-Programmable Analog Array for Wireless Sensing

Brandon Rumberg and David W. Graham
West Virginia University, Morgantown


ISQED 2014

Runtime 3-D Stacked Cache Data Management for Energy Minimization of 3-D Chip-Multiprocessors

Seunghan Lee(1) , Kyungsu Kang(2) , Jongpil Jung(1) , Chong-Min Kyung(1)
(1) Korea Advanced Institute of Science and Technology, Korea, (2) LSI Lab, EPFL, Lausanne, Switzerland


Statistical Methodology for Modeling Non-IID Memory Fails Events

Sabine Francis(1) , Rouwaida Kanj(1) , Rajiv Joshi(2) , Ayman Kayssi(1) , Ali Chehab(1)
(1) American University of Beirut, Beirut, Lebanon, (2) IBM, Yorktown Heights, New York, USA


ISQED 2013

Peak Power Reduction of a Sensor Network Processor Fabricated With Deeply Depleted Channel Transistors in 65nm Technology

Kentaro Kawakami, Takeshi Shiro, Hironobu Yamasaki, Katsuhiro Yoda, Hiroaki Fujimoto, Kenichi Kawasaki, Yasuhiro Watanabe
Fujitsu Laboratories Ltd.


Cost-effective 45nm 6T-SRAM Reducing 50mV Vmin and 53% Standby Leakage with multi-Vt Asymmetric Halo MOS and Write Assist Circuitry

Koji Nii(1), Makoto Yabuuchi(1), Hidehiro Fujiwara(1), Yasumasa Tsukamoto(1), Yuichiro Ishii(1), Tetsuya Matsumura(1), Yoshio Matsuda(2)
(1)Renesas Electronics Corporation, (2)Kanazawa University


LMgr: A Low-Memory Global Router with Dynamic Topology Update and Bending-Aware Optimum Path Search

Jingwei Lu(1) and Chiu-Wing Sham(2)
(1)University of California, San Diego, (2)The Hong Kong Polytechnic University


ISQED 2012

A Self-Testable SiGe LNA and Built-in-Self-Test Methodology for Multiple Performance Specifications of RF Amplifiers

Abhilash Goyal, Madhavan Swaminathan, Abhijit Chatterjee, Duane Howard, and John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology


Device- and System-Level Performance Modeling for Graphene P-N Junction Logic

Chenyun Pan and Azad Naeemi
School of Electrical and Computer Engineering
Georgia Institute of Technology


ISQED 2011

A Design Time Simulator for Computer Architects

Sangeetha Sudhakrishnan, Francisco J. Mesa Martinez, Jose Renau
University of California, Santa Cruz


Design and Analysis of Metastable-Hardened and Soft- Error Tolerant High-Performance, Low-Power Flip-Flops

David Li, David Rennie, Pierce Chuang, David Nairn, Manoj Sachdev
University of Waterloo, Canada


Complementary Nano-Electro-Mechanical Switch for Ultra-Low-Power Applications: Design and Modeling

Khawla Alzoubi(1), Daniel G. Saab(2), Massood Tabib-Azar(3), Sijing Han(2)
(1)Tafila Technical University, Jordan, (2)Case Western Reserve, (3)University of Utah


ISQED 2010

Robust Gate Sizing by Uncertainty Second Order Cone

Jin Sun, Janet Wang
Department of Electrical and Computer Engineering
The University of Arizona, Tucson, USA


Scalable Methods for the Analysis and Optimization
of Gate Oxide Breakdown

Jianxin Fang, Sachin S. Sapatnekar
Department of Electrical and Computer Engineering
University of Minnesota, Minneapolis, USA


UC-PHOTON: A Novel Hybrid Photonic network-on-Chip
for Multiple Use-Case Applications

Shirish Bahirat, Sudeep Pasricha
Electrical and Computer Engineering Department
Colorado State University, Fort Collins, USA


ISQED 2009

Small Embeddable NBTI Sensors (SENS) for Tracking On-Chip Performance Decay

Adam Cabe, Zhenyu Qi, Stuart Wooters, Travis Blalock, Mircea Stan          

University of Virginia


Power & Variability Test Chip Architecture and 45nm-Generation Silicon-Based

Analysis for Robust, Power-Aware SoC Design

Ramnath Venkatraman, Ruggero Castagnetti, Andres Teene, Benjamin Mbouombouo, Shiva Ramesh

LSI Corporation


3D-GCP: An Analytical Model for the Impact of Process Variations on the

Critical Path Delay Distribution of 3D ICs

Siddharth Garg and Diana Marculescu

Carnegie Mellon University

ISQED 2008

A methodology for characterization of large macro cells and IP blocks considering process variations
   Amit Goel(1), Sarma Vrudhula(1), Feroze Taraporevala(2), Praveen Ghanta(2)
             (1)Arizona State University, (2)Synopsys Inc.


Characterization of Standard Cells for Intra-Cell Mismatch Variations
  Savithri Sundareswaran(1), Jacob Abraham(2), Alexandre Ardelea(1), Rajendran Panda(1)
     (1)Freescale Semiconductor, (2)University of Texas at Austin


Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM)
    Yiran Chen, Xiaobin Wang, Hai Li, Hongyue Liu, Dimitar Dimitrov
Seagate LLC


ISQED 2007

Design of a Window Comparator with Adaptive Error Threshold for Online Testing Applications

Amit Laknaur, Rui Xiao, Sai Raghuram Durbha, Haibo Wang

Southern Illinois University, Carbondale


Assessing the Implications of Process Variations on Future Carbon Nanotube Bundle Interconnect Solutions

Arthur Nieuwoudt and Yehia Massoud

Rice University


A DOE Set for Normalization-Based Extraction of Fill Impact on Capacitances

Andrew B. Kahng and Rasit O. Topaloglu

University of California San Diego


ISQED 2006

Improving Transient Error Tolerance of Digital VLSI Circuits Using

Robustness Compiler (ROCO)

Chong Zhao, Sujit Dey

University of California At San Diego , La Jolla , Ca


System-Level SRAM Yield Enhancement

Fadi Kurdahi *, Ahmed Eltawil *, Rouwaida Kanj **, Young-Hwan Park *, Sani Nassif**

*UC Irvine, Irvine , CA , **IBM Austin Research Labs., Austin , TX


Power Gating with Multiple Sleep Modes

Kanak Agarwal*, Harmander Deogun**, Dennis Sylvester**, Kevin Nowka*

*IBM Research, Austin , TX , ** University of Michigan , Ann Arbor , MI


FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs

Bin Zhang, Wei-shen Wang, Michael Orshansky

University of Texas , Austin , TX


ISQED 2005

Noise Library Characterization for Large Capacity Static Noise Analysis Tools

    Alex Gyure, Alireza Kasnavi, Sam Lo, Peivand F. Tehrani, William Shu, Mahmoud Shahram, Joddy W. Wang, Jindrich Zedja

Synopsys Inc., Mountain View, CA


A Mask Reuse Methodology for Reducing System-on-a-Chip Cost

    Subhrajit Bhattacharya, John A. Darringer, Daniel L. Ostapko, Youngsoo Shin

IBM Corp., Yorktown Heights, NY


A New Method for Robust Design of Digital Circuits

    Dinesh Patil, Sunghee Yun, Seung-Jean Kim, Alvin Cheung, Mark     Horowitz, Stephen Boyd

Stanford University, Stanford, CA


A Min-Variance Iterative Method for Fast Smart Dummy Feature Density Assignment in Chemical-Mechanical Polishing

    Xin Wang, Charles Chiang, Jamil Kawa, Qing Su

Synopsys Inc., Mountain View, CA


ISQED 2004

SRAM Leakage Suppression by Minimizing Standby Supply Voltage
Huifang Qin, Yu Cao, Dejan Markovic, Andrei Vladimirescu, Jan Rabaey,
University of California at Berkeley


Scan BIST Targeting Transition Faults Using a Markov Source
Hangkyu Lee*, Irith Pomeranz*, Sudhakar M. Reddy**
*Purdue University, **University of Iowa


Application Specific Worst Case Corners using Response Surfaces and Statistical Models
Manidip Sengupta, Sharad Saxena, Lidia Daldoss, Glen Kramer, Sean Minehane, Jianjun Cheng
PDF Solutions


Robustness Enhancement through Chip-Package Co-Design for High-Speed Electronics
Meigen Shen, Li-Rong Zheng, Hannu Tenhunen
Royal Institute of Technology (KTH), Sweden


ISQED 2003

Design and Measurement of an Inductance-Oscillator for Analyzing Inductance Impact on On-Chip Interconnect Delay

Takashi Sato*, Hiroo Masuda**

*Hitachi, Ltd., Kyoto University,Tokyo, Japan, **Semiconductor Technology Academic Research Center, Kanagawa, Japan


ISQED 2002

Extending the Viability of ΙDDQ Testing ίη Deep Submicron Era Υ. Tsiatouhas, Integrated Systems Development

S.A., Athens, Greece Th. Haniotakis, Southem Illinois University, Carbondale, IL D. Nikolos, University of Patras, Patras, Greece Α. Arapoyanni, University of Athens, Athens, Greece


 Honorable Mention goes to the following papers:

Pre-route Noise estimation in Deep Submicron Integrated Circuits

Murat Becer, Motorola, Inc., Austin, ΤΧ David Blaauw, University of Michigan, Αnn Arbor, ΜΙ Rajendran Panda, Motorola, Inc., Austin, ΤΧ Ibrahim Ν. Hajj, University of Illinois, Urbana, IL

 

Measurement of lnherent Noise in EDA Tools

Andrew Β. Kahng, University of Califomia at San Diego, La Jolla, CA Stefanus Mantik, University of Califomia, Los Angeles, CA  


ISQED 2001

Color Counting and its Application to Path Delay Fault Coverage

Jayant Deodhar*, Spyros Tragoudas**

*Intel, **Southern Illinois University


A System for Automatic Recording and Prediction of Design Quality Metrics

Andrew B. Khang, Stefanus Mantik

UCLA


ISQED 2000

On Effective IDDQ Testing of Low Voltage CMOS Circuits Using Leakage Control Techniques

Zhanping Chen*, Liqiong Wei*,Kaushik Roy**

*Intel, Purdue University


Synthesis Experiments and Performance Metrics for Evaluating the Quality of IP Blocks and Megacells

Tomas Bautista and Antonio Nunez

University of Las Palmas de Gran Canaria


Quick On-Chip Self- and Mutual-Inductance Screen

Shen Lin, Norman Chang, Sam Nakagawa

Hewlett-Packard Laboratories



ISQED