For the transistor sizing of multistage digital circuits with predictable delays, the relationship between the effective input capacitances of all the stages and the stage size ratios must be known. Effective capacitances of the FinFET logic gates are strongly dependent on transition times at their input-output nodes and are, therefore, not directly proportional to the stage size, as opposed to conventional transistors. Due to this, the methods developed for transistor sizing of planar logic circuits are not valid for FinFET logic circuits. Though this effect is not present in highly gate-drain overlapped FinFET devices, their performance is highly compromised (higher power consumption and larger delay). We propose a modification of the existing logical effort based delay model for FinFET inverter chain that considers the above-mentioned characteristics of FinFET devices. We also discuss branching loads and transistor sizing of non-critical paths in this paper. We observe that our FinFET sizing scheme leads to a significant reduction in inverter chain delays. We observe that error in estimation of delay (not considering the transition time dependency) in a two stage FO4 inverter chain is 31.8% and 15.3% respectively (from mixed-mode TCAD simulations).