This paper describes a design methodology for a process variation aware D-Flip-Flop (DFF) using regression analysis. A DFF circuit is a key storage element in a digital CMOS circuit, and its delay strongly affects final circuit performance. It is common that a DFF circuit is carefully hand-crafted by an experienced designer and provided by a semiconductor foundry as a library cell. However, there are not enough discussions on how to design, and tune the transistor size inside a DFF to achieve better delay performance. Also, within-die random variation has a strong impact on the delay performance of a DFF, especially at low supply voltage. Since the delay performance of a DFF circuit strongly depends on the transistors consisting of it’s latch circuits and clock driver circuits, it is difficult to determine the performance-critical transistors inside a DFF. We propose to use a regression analysis to model the delay characteristics of a DFF and utilize the equation for transistor width tuning of the DFF circuit. Regression analysis can not only identify the performance-critical transistors inside the DFF, but also estimate its worst case performance under a process variation. The result of proposed design methodology is verified using a Monte-Carlo simulation. The result shows the proposed method achieves to design a DFF which has similar or better delay characteristics in comparison with the DFF designed by an experienced cell designer.