Verification Methodology to Guarantee Low Routing Resistance to Well Taps

MOHAMMED FAKHRUDDIN, Kuok-Khian Lo, James Karp, Michael Hart, Min-Hsing Chen
Xilinx, Inc.


Abstract The proposed verification methodology enables designers to meet a maximum resistance specification for the well taps routing. Key strengths of the flow are: automatic identification of both well taps and VDD/VSS grid; comparison of the extracted resistance to a user defined specification value; review of results with a graphical interface; no marker layers to identify the extraction path.