Off-Chip Test Architecture for Improving Multi-Site Testing Efficiency using Tri-State Decoder and 3V-Level Encoder

Sungyoul Seo1, Hyeonchan Lim1, Soyeon Kang1, Sungho Kang2
1Yonsei University, Seoul, Korea, 2Yonsei University


Over recent generations, multi-site testing became the trend in the semiconductor test technology. According to this trend, the solution using low-end automatic test equipment (ATE) and built off self-test (BOST) have been extensively researched in the field of memory test and logic test. Despite the success in the memory test, the logic test still has to solve some problems such as test pin counts, test data volume, etc. In this paper, we present a new off-chip test architecture for improving multi-site testing efficiency, which is composed of tri-state decoders and 3V-level encoders. It is useful to improve total test application time (TAT) by reducing the test pin counts and the test data volume. Moreover, this off-chip is easily compatible with the existing scan compression method. Experimental results show that this test architecture improves the multi-site testing efficiency by reducing about 20% with respect to the TAT on both International Symposium on Circuits and Systems (ISCAS)’89 and large International Test Conference (ITC)’99 benchmark circuits in all of cases compared to the previous works.