CMOS scaling improves transistor density and lower the cost per transistor at a cost to other factors. Tall, narrowly spaced wires have made lateral coupling capacitance dominant for the deeply scaled CMOS back-end-of-line (BEOL) metals, which impacts worst-case timing and noise. Narrow wires further impact electromigration, yield and reliability. Since the densest routing does not certainly provide the best overall design quality, we systematically evaluate the impacts of relaxing the BEOL (r-BEOL) pitch. To implement sample designs, we used a commercial 28 nm CMOS technology and standard physical synthesis tools. Evaluation of these sample 28 nm designs show that relaxing the pitch brings improved signal integrity, designfor- manufacturability (DFM), and timing closure, at modest cost to area and no cost to performance. This suggests that r- BEOL might be a more optimal approach for low and medium volume products where the design and masks cost can dominate the cost of the wafers.