This paper discusses the back-end-of-the-line (BEOL) layers for a 7 nm predictive process design kit (PDK). The rationale behind choosing a particular lithographic process— EUV lithography, self-aligned double patterning (SADP), and litho-etch litho-etch (LELE)—for each group of layers, in addition to some design rule values, is described. The rules are based on the literature and on design and technology cooptimization (DTCO) evaluation of standard cell based designs and automated place-and-route experiments. For SADP layers, the layouts are decomposed into the requisite masks for validation. Edge placement errors, misalignment, and critical dimension uniformity are included in the analysis. Margins to prevent time-dependent dielectric breakdown (TDDB), are also comprehended in the design rules. All vias are self-aligned and merged depending on their configuration and alignment to limit constraints on metal spacing and standard cell pin accessibility.