This paper re-addresses standard-cell based SRAM design for sub-threshold operation. Rather than using flip-flop or latch gates to implement SRAM bitcells, a circuit structure that is fully based on combinational logic, OAI (Or-And-Invert) and AOI (And-Or-Invert) gates, is presented. Measurements on a 90-kb 40-nm SRAM chip show that, the OAI/AOI-based SRAM operates at a minimum access voltage of 410 mV and obtains a minimum read energy of 30 fJ per access per bit. At the data retention voltage of 330 mV, it features a leakage power of 1.6 pW per bit. Taking the proposed SRAM and a classic 6T-cell design as examples, the relationship between yield and bias in key figures of merit of a SRAM is highlighted based on silicon measurement results. This motivates a statistical view on the evaluation of SRAMs operating in sub-threshold.