In this paper, a new tool is proposed to provide a solution for the implementation of generic 3D Network-on-Chips (NoCs) to serve different applications. The proposed tool denoted by 3D-NOCET, is based on the 3D Direct-Elevator routing algorithm. The 3D-NOCET tool allows the user to create different combinations of 3D-NoCs based on the 2D-routing topology, number of tiers and number of routers per each tier through a fully automated process. That opens the door to perform future experimental evaluations for the different 3D-NoC structures. The future experimental evaluations and the performance comparative analyses help to ﬁnd the optimal network conﬁguration for different applications, speciﬁcally the 3D-NoC based Field Programmable Gate Arrays (FPGA).