Low Temperature Endurance Failures on Flash Memory

Steve Heinrich-Barna1, Clyde Dunn1, Douglas Verret2
1Texas Instruments, Inc, 2Texas Instruments, Inc (Retired)


Abstract – Write-erase cycling of flash memories has distinct failure signatures that have been thoroughly documented in the literature. A new mechanism has been uncovered when cycling at low temperatures. On the 65nm embedded flash technology, units exhibited a programming failure signature. However, further investigation verified that fail bits were fully programmed. Cause of failure was attributed to a non-classical hot carrier mechanism affecting an NMOS transistor in the sense circuitry. This was not expected as the Vds of the affected transistor was relatively low. TCAD simulations verified that the back bias on the transistor heated up electrons in the drain space charge region, generating secondary electrons from avalanche multiplication. The details of the failure mechanism, previously unpublished and unknown to current reliability tools, will be discussed and the corrective actions will be identified. Keywords: flash, endurance, transistor instability, channel hot carriers (CHC).