Design of gate-level monolithic three-dimensional integrated circuits (3-D ICs) requires 3-D placement, 3-D clock-tree synthesis, 3-D routing and monolithic inter-layer via insertion, 3-D timing and power optimization, and so on. Until now, however, various research on gate-level monolithic 3-D ICs focused on analysis of wirelength, power consumption, performance, thermal characteristics, etc. based on a design methodology using 2-D placement, uniform location scaling, z-directional partitioning, and 2-D planar legalization. However, the design of gate-level monolithic 3-D IC layouts requires more sophisticated 3-D algorithms to generate high-quality layouts. In this paper, we propose a legalization algorithm for the design of multi-tier gate-level monolithic 3-D ICs. The algorithm performs planar and z-directional legalization in an interleaved fashion to perform native 3-D legalization. We compare the proposed algorithm with the legalization algorithm being used in the literature and show that the proposed algorithm achieves shorter wirelength with almost no density constraint violation.