International Symposium on Quality Electronic Design (ISQED)
CFP
Submit Paper

Program at a Glance

Register
Sponsor/Exhibit

Press Room
Press Room

CalPT

ISQED 2015 Conference At-a-Glance

Monday, March 2, 2015

9:00am–4:30pm

ISQED 2015 Tutorials

Great America Meeting Room 3

 

The Frontiers of Robust Circuit Design in Sub-28nm Process Technologies
Jim Dodrill - ARM


Powering Microsystems
Prof. Gabriel A. Rincón-Mora - Georgia Tech


Reliability Challenges in Sub 20nm Technology
Dr. Tanya Nigam - GLOBALFOUNDRIES


Secure Hardware in the Nano Era: Some New Directions
Prof. Swarup Bhunia - Case Western


Security and Validation in SoC Designs - Cooperation, Conflicts, and Trade-offs
Dr. Sandip Ray - Intel Corporation


Neuromorphic Computing based Processors
Prof. Hao Jiang - San Francisco State University

Tuesday, March 3, 2015

8:50am–10:00am

Plenary Session 1P

Great America Ballroom

 

Keynote Speeches:

Rethinking Design Creation, Verification and Validation for the Internet of Things

George Zafiropoulos -Vice President of Solutions Marketing in the AWR Group , National Instruments


What's Really Driving the Internet of Things? – Insights on the Market, Technology and Challenges

Mike Ballard - Sr. Manager, Home Appliance Solutions and Smart Energy Groups , Microchip Technology

10:00am-10:20am

Morning Break

10:20am–12 Noon

Session 1A

Robust Memory Design

 

 

Great America Meeting Room 1

Session 1B

Advances in Physical Design & Optimization

 

Great America Meeting Room 2

Session 1C

Manufacturing, Modeling, and Design Issues in Nanoscale CMOS

 

Great America Meeting Room 3

12 Noon–1:30pm

ISQED Luncheon

Room: Silicon Valley

 

Best Paper Awards

Committee Recognition Awards

ISQED Fellow Award


Luncheon Panel Discussion

Industry Panel on Hardware and System Security

ARM, Intel, Microsemi, Cadence, Freescale

1:30pm–3:30pm

Session 2A

Voltage Regulators and Analog Design

Great America Meeting Room 1

Session 2B

Architectural Analysis and Algorithms

Great America Meeting Room 2

Session 2C

BIST and Scan Testing

 

Great America Meeting Room 3

3:30pm–3:50pm

Afternoon Break

3:50pm–5:30pm

Session 3A

Low Power Circuit Design

 

 

Great America Meeting Room 1

Session 3B

Energy and Power Management for IOT

 

Great America Meeting Room 2

Session 3C

Low-power and Robust Design Techniques

 

Great America Meeting Room 3

5:30pm–7:00pm

Poster Papers & Mixer

Room: Atrium

Wednesday, March 4, 2015

8:55am–10:00am

Plenary Session 2P

Great America Ballroom

 

Keynote Speeches:

From Cluster to Cloud: How to Harness the Internet of Things

Clodoaldo Barrera - Chief Technical Strategist , IBM


Connecting the Dots to achieve high Reliability and Quality

Raj N. Master - General Manager, Reliability, Quality and Silicon Operations , Microsoft

 
10:00am–10:20am

Morning Break

10:20am–12 Noon

Session 4A

Challenges in SOC Design

 

 

Great America Meeting Room 1

Session 4B

Network and Multiprocessing Systems

 

 

Great America Meeting Room 2

Session 4C

Verification and Delay Measurement

 

Great America Meeting Room 3

12 Noon–1:00pm

Lunch Break

1:00pm–3:00pm

Session 5A

Hardware and System Security

 

 

Great America Meeting Room 1

Session 5B

Systems Implementation and Optimization

 

Great America Meeting Room 2

Session 5C

Packaging and 3D Integration

'

 

Great America Meeting Room 3

3:00pm–3:20pm

Afternoon Break

3:20pm–5:00pm

Session 6A

Sensor Technology

 

 

 

Great America Meeting Room 1

Session 6B

EDA for Design Exploration & Analysis Beyond Moore's Law

 

Great America Meeting Room 2

Session 6C

Emerging Solid-State Device and Interconnect Technologies

 

Great America Meeting Room 3

 

Co-Located Events


ISQED