Synopsys, Inc. (Nasdaq:SNPS) is the world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys’ comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, software-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk.
Mentor Graphics is a world leader in EDA products, consulting services and award-winning support for electronics and semiconductor companies. Mentor offers solutions that meet the demand for short design cycle time, improved productivity, and acceptable yield, including tools for IC physical design, physical signoff, yield enhancement and testing of sub-nanometer ICs. Products include the Olympus-SoC place and route system with multi-corner multimode design closure, the Calibre physical verification suite with equation-based DRC, Calibre DFM solutions for random, systematic, and parametric issues affecting yield, and the comprehensive Tessent suite for production test, built-in self test, failure diagnosis and accelerated yield learning.
Cadence is the global EDA leader in software, hardware, IP and services that is driving the transformation of the electronics industry. With a focus on EDA360, Cadence embraces the entire spectrum of the design process, improving end-product profitability for customers. The company supports an application-driven approach for creating, integrating, and optimizing designs that helps customers realize silicon chips, system-on-chip devices, and complete systems at lower costs and with higher quality. Cadence is headquartered in San Jose, Calif., with sales offices and design centers around the world to serve the electronics industry. Learn more at www.cadence.com
Exhibiting ChipTimer, design reoptimization and timing closure tool. It improves clock speed by ~30-200%, reduces area by ~10-30% and leakage power by several factors. Using design-specific library cells derived from existing library as necessary, works for all processes.
Si2 is the largest organization of industry-leading semiconductor, systems, EDA and manufacturing companies focused on the development and adoption of standards to improve the way integrated circuits are designed and manufactured, in order to speed time-to market, reduce costs, and meet the challenges of sub-micron design. Now in its 23rd year, Si2 is uniquely positioned to enable timely collaboration through dedicated staff and a strong implementation focus driven by its member companies. Si2 represents nearly 100 companies involved in all parts of the silicon supply chain throughout the world. See http://www.si2.org
What if you knew the temperature profile inside your chip—before tapeout? Today’s high performance chips have areas with very high power density, causing temperature to rise unevenly within the die. Smaller form factors make it harder to remove the heat. Gradient’s HeatWave™ thermal simulator produces a full-chip, three-dimensional temperature profile at device- and interconnect-level resolution. Instance-specific temperatures are annotated into your netlist, giving you thermally-accurate electrical analysis. The designer can pinpoint hotspots and excessive temperature variations—and avoid thermally-induced circuit failures, performance degradations, and reliability issues—before building the chip.
Low Power Design is the engineer's portal to green design. We cover the green angle in our news section in order to increase our reader's awareness of the importance of the work they're doing. But at heart we're a design book, trying to provide the tools to help our readers get their job done. Low-Power Design deliberately picked up the torch from Portable Design, which was all about energy efficient design. Looking at the macro-level implications—as evidenced by the data center example above—we realized that “green engineering” is all about creating energy-efficient designs. The power management techniques first developed for portable devices apply equally well to their plugged-in brethren. Now we won’t ignore you if your product doesn’t run off a battery. In fact you get bonus points if it uses less power than the state of Massachusetts (Rhode Island, even)!
Silicon Valley Technical Institute is an educational organization providing certificate training programs covering various aspects of electronic design, design automation, semiconductor technology & manufacturing, computer, communications engineering, and Internet technologies. Through an advanced, relevant, and timely database of training courses and programs, SVTI provides students the opportunity to gain a comprehensive grasp of concepts in a shorter period of time, to remain up to date in their field, and/or to acquire the technical knowledge to begin or advance their career. Our unique method of high student-instructor interaction further ensures that students receive the support and guidance essential in producing an effective and lasting educational experience. As a leading provider of certificate training programs and training courses, by training and supporting high-tech professionals and with the assistance of an industry advisory council, consisting of industry and academia experts, we strive to maintain a bridge between those seeking to enhance or launch a career and employers.