Chair: Dinesh Somasekhar
Co-Chair: Haibo Wang

10:30AM
1B.1
A Radiation Hardened Nano-power 8Mb SRAM in 130nm CMOS
Mark Lysinger¹,  Francois Jacquet²,  David Mcclure¹,  Philippe Roche²,  Mehdi Zamanian¹,  Naren Sahoo¹,  John Russell^1
1STMicroelectronics, Carrollton, USA, ²STMicroelectronics, Crolles, France

11:00AM
1B.2
Error-Tolerant SRAM Design for Ultra-Low Power Standby Operation
Huifang Qin¹,  Animesh Kumar¹,  Kannan Ramchandran¹,  Jan Rabaey¹,  Prakash Ishwar^2
1University of California, Berkeley, ²Boston University

11:20AM
1B.3
Error Protected Data Bus Inversion Using Standard DRAM Components
Maurizio Skerlj¹ and Paolo Ienne^2
1Qimonda AG, ²EPFL

11:40AM
1B.4
Process Variation Aware Bus-coding scheme for Delay Minimization in VLSI Interconnects
Raghunandan Chittarsu,  Sainarayanan K S,  Srinivas M B
IIIT Hyderabad

Chair: Masahiro Fujita
Co-Chair: Peter Oshea

10:30AM
1C.1
Speed-up of ASICs derived from FPGAs by Transistor Network Synthesis Including Reordering
Tiago Cardoso¹,  Leomar Rosa Jr.¹,  Felipe Marques¹,  Renato Ribas¹,  Andre Reis^2
1UFRGS, ²Nangate

11:00AM
1C.2
Fast and Accurate Waveform Analysis with Current Source Models
Vineeth Veetil,  Dennis Sylvester,  David Blaauw
University of Michigan

11:20AM
1C.3
An Efficient Method for Fast Delay and SI Calculation Using Current Source Models
Xin Wang,  Ali Kasnavi,  Harold Levy
Synopsys Inc.

11:40AM
1C.4
Adaptive Stochastic Collocation Method (ASCM) for Parameterized Statistical Timing Analysis with Quadratic Delay Model
Yi Wang¹,  Xuan Zeng¹,  Wei Cai²,  Hengliang Zhu¹,  Xu Luo^1
1State Key Lab. of ASIC & System, Microelectronics Dept., Fudan University, ²Depart. of Mathematics, University of North Carolina at Charlotte

Chair: Keith Bowman
Co-Chair: Yu Cao

10:30AM
1D.1
Combinational Logic Circuit Protection Using Customized Error Detecting and Correcting Codes
Avijit Dutta¹ and Abhijit Jas^2
1Mentor Graphics, ²Intel Corp

11:00AM
1D.2
Output Remapping Technique for Soft-Error Rate Reduction in Critical Path
Qian Ding,  Yu Wang,  Hui Wang,  Rong Luo,  Huazhong Yang
Tsinghua University, Beijing

11:20AM
1D.3
IR Drop Reduction via a Flip-Flop Resynthesis Technique
Tsung-Yi Wu,  Jiun-Kuan Wu,  Liang-Ying Lu,  Kuang-Yao Chen,  Meng-Lin Xie
National Changhua University of Education

11:40AM
1D.4
Noise Interaction Between Power Distribution Grids and Substrate
Daniel A. Andersson¹,  Simon Kristiansson²,  Kjell O. Jeppson²,  Lars 'J' Svensson²,  Per Larsson-Edefors^2
1Department of Computer Science and Engineering, Chalmers University of Technology, ²

Chair: Masanori Hashimoto
Co-Chair: David Pan

1:30PM
2A.1
Fundamental Data Retention Limits in SRAM Standby -- Experimental Results
Animesh Kumar¹,  Huifang Qin¹,  Prakash Ishwar²,  Jan Rabaey¹,  Kannan Ramchandran^1
1EECS, University of California, Berkeley, CA, ²ECE, Boston University, Boston, MA

2:00PM
2A.2
Quality of a Bit (QoB): A New Concept in Dependable SRAM
Hidehiro Fujiwara,  Shunsuke Okumura,  Yusuke Iguchi,  Hiroki Noguchi,  Yasuhiro Morita,  Hiroshi Kawaguchi,  Masahiko Yoshimoto
Kobe University

2:30PM
2A.3
Cache Design for Low Power and High Yield
Baker Mohammad¹,  Martin Saint Laurent¹,  Paul Bassett²,  Jacob Abraham^2
1Qualcomm, ²The University of Texas at Austin

2:50PM
2A.4
Projection-Based Piecewise-Linear Response Surface Modeling for Strongly Nonlinear VLSI Performance Variations
Xin Li¹ and Yu Cao^2
1Carnegie Mellon University, ²Arizona State University

3:10PM
2A.5
High Output Resistance and Wide Swing Voltage Charge Pump Circuit
Tian Xia¹, Stephen Wyatt²

¹University of Vermont, ²IBM

Chair: Mark Budnik
Co-Chair: Sarma Vrudhala

1:30PM
2B.1
Interconnect Signaling and Layout Optimization to Manage Thermal Effects Due to Self Heating in On-Chip Signal Buses
Krishnan Sundaresan¹ and Nihar Mahapatra^2
1Sun Microsystems, Inc., ²Michigan State University

2:00PM
2B.2
A Low-Power Double_Edge_Triggered Address Pointer Circuit for FIFO Memory Design
Saravanan Ramamoorthy¹,  Haibo Wang¹,  Sarma Vrudhula^2
1Southern Illinois University, Carbondale, ²Arizona State University, Tempe

2:30PM
2B.3
Minimizing Offset for Latching Voltage-Mode Sense Amplifiers for Sub-threshold Operation
Joseph Ryan and Benton Calhoun
University of Virginia

2:50PM
2B.4
Dependence of Minimum Operating Voltage (VDDmin) on Block Size of 90-nm CMOS Ring Oscillators and Its Implications in Low Power DFM
Taro Niiyama¹,  Piao Zhe¹,  Koichi Ishida¹,  Masami Murakata²,  Makoto Takamiya¹,  Takayasu Sakurai^1
1University of Tokyo, ²STARC

3:10PM
2B.5
Accurate Temperature Estimation for Efficient Thermal Management
Shervin Sharifi,  Chunchen Liu,  Tajana Rosing
University of California, San Diego

Chair: Murat Becerr
Co-Chair: He Jin

1:30PM
2C.1
Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS Logic
Kumar Yelamarthi and Henry Chen
Wright State University

2:00PM
2C.2
Compact Variation-Aware Standard Cell Models for Timing Analysis -- Complexity and Accuracy Analysis
Seyed-Abdollah Aftabjahani and Linda Milor
Georgia Institute of Technology

2:30PM
2C.3
A Statistical Characterization of CMOS Process Fluctuations in Subthreshold Current Mirrors
Lei Zhang,  Zhiping Yu,  Xiangqing He
Institute of Microelectronics, Tsinghua University

2:50PM
2C.4
Robust Estimation of Timing Yield with Partial Statistical Information on Process Variations
Lin Xie and Azadeh Davoodi
University of Wisconsin

3:10PM
2C.5
Variation Aware Spline Center and Range Modeling for Analog Circuit Performance
Shubhankar Basu,  Balaji Kommineni,  Ranga Vemuri
University of Cincinnati

Chair: Sao-Jie Chen
Co-Chair: Fadi Kurdahi

3:45PM
3A.1
High-quality Circuit Synthesis for Modern Technologies
Lech Jozwiak¹,  Artur Chojnacki²,  Aleksander Slusarczyk^1
1Eindhoven University of Technology, ²PDF Solutions Inc.

4:15PM
3A.2
ILP based Gate Leakage Optimization using DKCMOS Library during RTL Synthesis
Saraju Mohanty
University of North Texas

4:45PM
3A.3
Improving the Efficiency of Power Management Techniques by Using Bayesian Classification
Hwisung Jung and Massoud Pedram
University of Southern California

5:05PM
3A.4
An On-Demand Test Triggering Mechanism for NoC-Based Safety-Critical Systems
Jason Lee,  Nikhil Gupta,  Praveen Bhojwani,  Rabi Mahapatra
Texas A&M University

5:25PM
3A.5
Constant Rate Dataflow Model with Intermediate PortsforEfficient Code Synthesis with Top-down design and Dynamic Behavior
Hyunok Oh
ARM Inc.

Chair: James Lei
Co-Chair: Mark Budnik

3:45PM
3B.1
Thermal-aware IR drop analysis in large power grid
Yu Zhong and Martin D. F. Wong
Univ. of Illinois at Urbana-Champaign

4:15PM
3B.2
A methodology for characterization of large macro cells and IP blocks considering process variations
Amit Goel¹,  Sarma Vrudhula¹,  Feroze Taraporevala²,  Praveen Ghanta^2
1Arizona State University, ²Synopsys Inc.

4:45PM
3B.3
Investigation of Process Impact on Soft Error Susceptibility of Nanometric SRAMs using a Compact Critical Charge Model
Shah M. Jahinuzzaman,  Mohammad Sharifkhani,  Manoj Sachdev
University of Waterloo

5:05PM
3B.4
Characterization of Standard Cells for Intra-Cell Mismatch Variations
Savithri Sundareswaran¹,  Jacob Abraham²,  Alexandre Ardelea¹,  Rajendran Panda^1
1Freescale Semiconductor, ²University of Texas at Austin

5:25PM
3B.5
Full-Chip Leakage Verification for Manufacturing Considering Process Variations
Tao Li and Zhiping Yu
Institute of Microelectronics, Tsinghua University

Chair: Tao Feng
Co-Chair: Patra Priyadarshan

3:45PM
3C.1
Processor Verification with hwBugHunt
Sangeetha Sudhakrishnan, Liying Su and Jose Renau
University of California, Santa Cruz

4:15PM
3C.2
Enhancing the Testability of RTL Designs Using Efficiently Synthesized Assertions
Mohammad Reza Kakoee, Mohammad Riazati, Siamak Mohammadi
Tehran University, IRAN

4:45PM
3C.3
Efficient Selection of Observation Points for Functional Tests
Jian Kang¹,  Sharad Seth¹,  Yi-Shing Chang²,  Vijay Gangaram^2
1University of Nebraska - Lincoln, ²Intel Corporation

5:05PM
3C.4
A Novel Test Generation Methodology for Adaptive Diagnosis
Rajsekhar Adapa,  Edward Flanigan,  Spyros Tragoudas
Southern Illinois University

5:25PM
3C.5
Timing-Aware Multiple-Delay-Fault Diagnosis
Vishal Mehta¹,  Malgorzata Marek-Sadowska¹,  Kun-Han Tsai²,  Janusz Rajski^2
1University of California Santa Barbara, ²Mentor Graphics Corporation

Chair: He Jin
Co-Chair: Miroslav Velev

E1.1
A Dual Oxide CMOS Universal Voltage Converter for Power Management in Multi-$V_{DD}$ SoCs
Dhruva Ghai,  Saraju Mohanty,  Elias Kougianos
University of North Texas

E1.2
Dominant Substrate Noise Coupling Mechanism for Multiple Switching Gates
Emre Salman¹,  Eby Friedman¹,  Radu Secareanu²,  Olin Hartin^2
1University of Rochester, ²Freescale Semiconductor

E1.3
A Statistic-based Approach to Testability Analysis
Chuang-Chi Chiou,  Chun-Yao Wang,  Yung-Chih Chen
National Tsing Hua University

E1.4
Generic Carrier-Based Core Model for Undoped Four-Terminal Double-Gate MOSFET Valid for Symmetric, Asymmetric, SOI, and Independent Gate Operation Modes
feng liu¹,  jin he¹,  wei bian¹,  yue fu¹,  jie feng¹,  xing zhang¹,  mansun chan^2
1institute of Microelectronics, peking university, ²ECE, Hongkong university of Science and technology

E1.5
On the Feasibility of Obtaining a Globally Optimal Floorplanning for an L-shaped Layout Problem
Tsu-Shuan Chang¹,  Manish Kumar²,  Teng-Sheng Moh³,  Chung-Li Tseng^4
1University of California, Davis, ²University of Missouri-Rolla, ³San Jose State University, ⁴University of New South Wales, Sydney

E1.6
Architecting for Physical Verification Performance and Scaling
John Ferguson and Robert Todd
Mentor Graphics

E1.7
Efficient Thermal Aware Placement Approach Integrated With 3D DCT Placement Algorithm
Haixia Yan,  Qiang Zhou,  Xianlong Hong
Computer Science and Technology Department,Tsinghua University

E1.8
CMOS based low cost Temperature Sensor
Neehar Jandhyala,  Lili He,  Morris Jones
San Jose State University

E1.9
An SSO Based Methodology for EM Emission Estimation from SoCs
Jairam S¹,  Stalin ###¹,  Jean-Yves Oberle²,  Udayakumar H^1
1TI India, ²TI France

E1.10
Statistical Data Stability and Leakage Evaluation of FinFET SRAM Cells with Dynamic Threshold Voltage Tuning under Process Parameter Fluctuations
Zhiyu Liu,  Sherif Tawfik,  Volkan Kursun
UW-Madison

E1.11
Characterization of New Static Independent-Gate-Biased FinFET Latches and Flip-Flops under Process Variations
Sherif Tawfik and Volkan Kursun
University of Wisconsin-Madison

E1.12
A Low Energy Two-step Successive Approximation Algorithm for ADC design
Ricky Yiu-kee Choi and Chi-ying Tsui
The Hong Kong University of Science and Technology

E1.13
Automated Specific Instruction Customization Methodology for Multimedia Processor Acceleration
Kang Zhao¹,  Jinian Bian¹,  Sheqin Dong¹,  Yang Song²,  Satoshi Goto^2
1Tsinghua University, China, ²Waseda University, Japan

Chair: Jayanta Bhadra
Co-Chair: José Silva Matos

1:30PM
2E.1
Process Variability Analysis in DSM Through Statistical Simulations And Its Implications To Design Methodologies
Srinivasa R STG,  Srivatsava Jandhyala,  Tondamuthuru R Narahari
Intel

1:34PM
2E.2
Parasitic Aware Process Variation Tolerant Voltage Controlled Oscillator (VCO) Design
Dhruva Ghai,  Saraju Mohanty,  Elias Kougianos
University of North Texas

1:38PM
2E.3
Evaluation of the PTSI Crosstalk Noise Analysis Tool and Development of an Automated Spice Correlation Suite to Enable Accuracy Validation
Venugopal Chakravarthy¹,  Jagganath Rao¹,  Prashanth Soraiyur^2
1S J College of Engg, Mysore-6, ²TI (India), Banga;lore

1:42PM
2E.4
Hotspot Based Yield Prediction with Consideration of Correlations
Qing Su,  Charles Chiang,  Jamil Kawa
Synopsys

1:46PM
2E.5
A Randomized Greedy Algorithm for the Pattern Fill Problem for DFM Applications
Maharaj Mukherjee¹ and Kanad Chakraborty^2
1IBM Corporation, ²Cypress Semiconductor Corporation

1:50PM
2E.6
A Passive 915 MHz UHF RFID Tag
José Palma,  César Marcon,  Fabiano Hessel,  Eduardo Bezerra,  Guilherme Rohde,  Carlos Reif,  Luciano Azevedo,  Carolina Metzler
PUCRS

1:54PM
2E.7
Crosstalk noise variation assessment and analysis for the worst process corner
Jae-Seok Yang and Andrew Neureuther
UC Berkeley

1:58PM
2E.8
DFM Based Detailed Routing Algorithms for ECP and CMP
Yin Shen,  Yici Cai,  Qiang Zhou,  Xianlong Hong
Department of Computer Science and Technology, Tsinghua University

2:02PM
2E.9
Instruction Scheduling for Variation-originated Variable Latencies
Toshinori Sato¹ and Shingo Watanabe^2
1Kyushu University, ²Kyushu Institute of Technology

2:06PM
2E.10
Hotspot Prevention Using CMP Model in Design Implementation Flow
Norma Rodriguez¹,  Li Song²,  Shishir Shroff²,  Kunanghan Chen²,  Taber Smith²,  Wilbur Luo^2
1AMD, ²Cadence

2:10PM
2E.11
The Statistical Failure Analysis for the Design of Robust SRAM in nano-scale Era
Young-Gu Kim,  Soo-Hwan Kim,  Hoon Lim,  Sanghoon Lee,  Keun-Ho Lee,  Young-Kwan Park,  Moon-Hyun Yoo
Samsung Electronics Co. Ltd

2:14PM
2E.12
Computation of Waveform Sensitivity using Geometric Transforms for SSTA
Ratnakar Goyal,  Harindranath Parameswaran,  Sachin Shrivastava
Cadence Design Systems

2:18PM
2E.13
On Efficient and Robust Constraint Generation for Layout Legalization
Sambuddha Bhattacharya¹,  Shabbir Batterywala¹,  Subramaniam Rajagopalan¹,  Tony Ma²,  Narendra Shenoy^2
1Synopsys (India) Pvt. Ltd., ²Synopsys Inc.

2:22PM
2E.14
Feedback-Switch Logic (FSL): A High-Speed Low-Power Differential Dynamic-Like Static CMOS Circuit Family
Charbel Akl and Magdy Bayoumi
university of louisiana at lafayette

2:26PM
2E.15
Analysis of System-Level Reliability Factors and Implications on Real-time Monitoring Methods for Oxide Breakdown Device Failures
Eric Karl,  David Blaauw,  Dennis Sylvester
University of Michigan

2:30PM
2E.16
Characterizing the Impact of Substrate Noise on High-Speed Flash ADCs
Parastoo Nikaeen,  Boris Murmann,  Robert Dutton
Stanford University

2:34PM
2E.17
Analytical Noise-Rejection Model Based on Short Channel MOSFET
Vinay Jain¹ and Payman Zarkesh-Ha^2
1IIT Kanpur, India, ²University of New Mexico, Albuqueruqe, NM

2:38PM
2E.18
A High-Performance Bus Architecture for Strongly Coupled Interconnects
Michael N Skoufis¹,  Kedar Karmarkaran¹,  Themistoklis Haniotakis²,  Spyros Tragoudas^1
1Southern Illinois University, ²University of Patras

2:42PM
2E.19
A Fully Integrated 2.4 GHz Mismatch-Controllable RF Front-end Test Platform in 0.18µm CMOS
Zahra sadat Ebadi and Resve Saleh
University of British Columbia

2:46PM
2E.20
A Holistic Approach to SoC Verification
Alicia Strang¹,  David Potts¹,  Shankar Hemmady^2
1Marvell Semiconductor, ²Synopsys

2:50PM
2E.21
A Robust and Efficient Pre-Silicon Validation Environment for Mixed-Signal Circuits on ####### Test Chips
Nathaniel August
Intel Corporation

2:54PM
2E.22
Hybrid Integration of Bandgap Reference Circuits using Silicon ICs and Germanium Devices
Jae Wook Kim,  Boris Murmann,  Robert Dutton
Stanford University

2:58PM
2E.23
VERIFICATION OF IP-CORE BASED SoC's
Anil Deshpande
Conexant Systems

3:02PM
2E.24
Innovative Test Solutions for Pin-Limited Microcontrollers
Matthew Stout and Kenneth Tumin
Freescale Semiconductor

3:06PM
2E.25
XStatic: A Simulation based ESD Verification and Debug environment
GANESH SHAMNUR and RAJESH BERIGEI
NATIONAL SEMICONDUCTOR CORPORATION

3:10PM
2E.26
Statistical Crosstalk Noise Analysis Using First Order Parameterized Approach for Aggressor Grouping
Sachin Shrivastava and Harindranath Parameswaran
Cadence Design Systems, India

3:14PM

2E.27
A Systematic Approach to Modeling and Analysis of Transient Faults in Logic Circuits
Natasa Miskov-Zivanov and Diana Marculescu
Carnegie Mellon University

Chair: Andre Reis
Co-Chair: Anand Iyer

3:45PM
3E.1
Cell Swapping Based Migration Methodology for Analog and Custom Layouts
Shabbir Batterywala¹,  Sambuddha Bhattacharya¹,  Subramanian Rajagopalan¹,  Tony Ma²,  Narendra Shenoy^2
1Synopsys (India) Pvt. Ltd., ²Synopsys Inc.

3:49PM
3E.2
a knowledge-based tool for generating and verifying hardware-ready embedded memory models
Paul Cheng
Cadence Design Systems

3:53PM
3E.3
"System Verilog for Quality of Results (QoR)"
Ravi Surepeddi
Magma Design Automation Inc

3:57PM
3E.4
Power Delivery System: Sufficiency, Efficiency, and Stability
Zhen Mu
Cadence Design Systems, Inc.

4:01PM
3E.5
Thermal Aware Global Routing of VLSI Chips for Enhanced Reliability
Aseem Gupta¹,  Fadi Kurdahi¹,  Nikil Dutt¹,  Kamal Khouri²,  Magdy Abadir^2
1University of California Irvine, ²Freescale Seminconductor

4:05PM
3E.6
Clock Skew Analysis via Vector-Fitting in Frequency Domain
Ling Zhang¹,  Haikun Zhu²,  Wanping Zhang²,  Wenjian Yu³,  Chung-Kuan Cheng^1
1UCSD, ²Qualcomm, ³Tsinghua University

4:09PM
3E.7
An Approach for A Comprehensive QA methodology for the PDKs
Sridhar Joshi,  Ravi Perumal,  Kamesh Gadepally,  Mark Young
National Semiconductor Corporation

4:13PM
3E.8
Strategies for Quality CAD PDKs
Kamesh Gadepally,  Mark Young,  James Lin,  Andy Franklin,  Ravi Perumal,  Sridhar Joshi
National Semiconductor Corporation

4:17PM
3E.9
Variability Analysis for Sub-100 nm PD/SOI Sense-Amplifier
Saibal Mukhopadhyay¹,  Rajiv Joshi²,  Keunwoo Kim²,  Ching-Te Chuang^2
1Georgia Institute of Technology, ²IBM T. J. Watson Research Center

4:21PM
3E.10
Predictive Delay Evaluation on Emerging CMOS Technologies: A Simulation Framework
Manuel SELLIER¹,  Jean-Michel PORTAL²,  Bertrand BOROT¹,  Steve COLQUHOUN¹,  Richard FERRANT¹,  Frédéric BŒUF¹,  Alexis FARCY^1
1STMicroelectronics, ²L2MP

4:25PM
3E.11
Process Variation Characterization and Modeling of Nanoparticle Interconnects for Foldable Electronics
Rasit Onur Topaloglu
University of California at San Diego

4:29PM
3E.12
A Simplified Model of Carbon Nanotube Transistor with Applications to Analog and Digital Design
Saurabh Sinha,  Asha Balijepalli,  Yu Cao
Arizona State University

4:33PM
3E.13
Adaptive Branch and Bound using SAT to Estimate False Crosstalk
Murthy Palla¹,  Jens Bargfrede¹,  Klaus Koch¹,  Walter Anheier²,  Rolf Drechsler^2
1Infineon Technologies AG, Munich, ²University of Bremen, Bremen

4:37PM
3E.14
Minimum Shield Insertion on Full-Chip RLC Crosstalk Budgeting Routing
Peng-Yang Hung,  Ying-Shu Lou,  Yih-Lang Li
National Chiao-Tung University

4:41PM
3E.15
Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution
Shinya Abe,  Masanori Hashimoto,  Takao Onoye
Osaka University

4:45PM
3E.16
A Novel Cell-Based Heuristic Method for Leakage Reduction in Multi-Million Gate VLSI Designs
Sandeep Gupta,  Jaya Singh,  Abhijit Roy
Texas Instruments(India) Pvt Ltd

4:49PM
3E.17
Study on the Silicon-Germanium Nanowire MOSFETs with the Core-Shell Structure
Yue Fu,  Jin He,  Feng Liu,  Jian Zhang,  Lining Zhang,  Xing Zhang
The Hub of Multi-Project-Wafer(MPW), School of Electronic Engineering and Computer Science, Peking University, Beijing 100871,P.R. China

4:53PM
3E.18
Elastic Timing Scheme for Energy-Efficient and Robust Performance
Rupak Samanta¹,  Ganesh Venkataraman²,  Nimay Shah¹,  Jiang Hu^1
1Texas A&M University, ²Magma

4:57PM
3E.19
Statistical Models and Frequency-Dependent Corner Models for Passive Devices
Ning Lu
IBM

5:01PM
3E.20
A thermal-friendly load-balancing technique for multi-core processors
Enric Musoll
ConSentry Networks

5:05PM
3E.21
Analytical Model for the Propagation Delay of Through Silicon Vias
DiaaEldin Khalil¹,  Yehea Ismail¹,  Muhammad Khellah²,  Tanay Karnik²,  Vivek De^2
1EECS Department, Northwestern University, ²Circuits Research Lab, Intel Corporation

5:09PM
3E.22
Sampling Error Estimation in High-Speed Sampling Systems Introduced by the Presence of Phase Noise in the Sampling Clock
Salam Marougi
Agilent Technologies

5:13PM
3E.23
A QoS Scheduler for Real-Time Embedded Systems
David Matschulat,  César Marcon,  Fabiano Hessel
PUCRS

5:17PM
3E.24
FPGA-Based 1.2 GHz Bandwidth Digital Instantaneous Frequency Measurement Receiver
Henry Chen
WSU

5:21PM
3E.25
A Tunable Clock Buffer for Intra-die PVT Compensation in Single-Edge Clock (SEC) Distribution Networks
Jeff Mueller and Resve Saleh
University of British Columbia

5:25PM
3E.26

Fast Timing Update under the Effect of IR Drop
muzhou shao
Synopsys Inc.

Chair: Kamesh Gadepally
Co-Chair: Lalitha Immaneni

10:30AM
4A.1
System-in-Package Technology: Opportunities and Challenges
Anna Fontanelli
Mentor Graphics Corporation

11:00AM
4A.2
Printed Circuit Board Assembly Test Process and Design for Testability
Thao Nguyen and Navid Rezvani
NetApp Inc.

11:20AM
4A.3
Fast Evaluation Method for Transient Hot Spots in VLSI ICs in Packages
Je-Hyoung Park¹,  Ali Shakouri¹,  Sung-Mo Kang^2
1UC Santa Cruz, ²UC Merced

11:40AM
4A.4
An Implementation of Performance-Driven Block and I/O Placement for Chip-Package Codesign
Ming-Fang Lai and Hung-Ming Chen
Dept of EE, NCTU, Taiwan

12:00PM
4A.5
Techniques for Early Package Closure in System-in-Packages
Santhosh Vaidyanathan,  Amit Brahme,  Jairam Sukumar
Texas Instruments,India

Chair: Bao Liu
Co-Chair: Soroush Abbaspour

11:00AM
4C.2
Fast Shape Optimization of Metallization Patterns for DMOS Based Driver
BO YANG,  Shigetoshi NAKATAKE,  Hiroshi MURATA
The University of Kitakyushu, Japan

11:20AM
4C.3
MAISE: An Interconnect Simulation Engine for Timing and Noise Analysis
Frank Liu and Peter Feldmann
IBM

11:40AM
4C.4
Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding
Xiaoji Ye¹,  Min Zhao²,  Rajendran Panda³,  Peng Li¹,  Jiang Hu^1
1Texas A&M University, ²Magma Design Automation, Inc., ³Freescale Semiconductor, Inc.

Chair: Sreejit Chakravarty
Co-Chair: Li-C Wong

10:30AM
4D.1
Sequential Path Delay Fault Identification Using Encoded Delay Propagation Signatures
Edward Flanigan,  Arkan Abdulrahman,  Spyros Tragoudas
Southern Illinois University

11:00AM
4D.2
2D Decomposition Sequential Equivalence Checking of System Level and RTL Descriptions
Dan Zhu,  Tun Li,  Yang Guo,  Si-kun Li
School of Computer Science and Technology, National University of Defense Technology

11:20AM
4D.3
Automated Standard Cell Library Analysis for Improved Defect Modeling
Jason Brown and Shawn Blanton
Carnegie Mellon University

11:40AM
4D.4
A Novel Automated Scan Chain Division Method for Shift and Capture Power Reduction in Broadside At-Speed Test
Ho Fai Ko and Nicola Nicolici
McMaster University

Chair: Rajeev Murgai
Co-Chair: Martin Wong

1:30PM
5A.1
Finite-Point Gate Model for Fast Timing and Power Analysis
Dinesh Ganesan¹,  Alex Mitev²,  Yu Cao¹,  Janet Wang^2
1Arizona State University, ²University of Arizona

2:00PM
5A.2
Noise-Aware On-Chip Power Grid Considerations Using a Statistical Approach
Daniel A. Andersson¹,  Lars 'J' Svensson²,  Per Larsson-Edefors^2
1Department of Computer Science and Engineering, Chalmers, ²

2:30PM
5A.3
Simulation and Measurement of On-Chip Supply Noise in Multi-Gigabit I/O Interfaces
Hai Lan¹,  Ralf Schmitt¹,  Chuck Yuan^2
1Rambus Inc., ²Rambus Ins.

2:50PM
5A.4
Practical Clock Tree Robustness Signoff Metrics
Anand Rajaram,  Raguram Damodaram,  Arjun Rajagopal
DDSP, Texas Instruments, Dallas

3:10PM
5A.5
Hierarchical Soft Error Estimation Tool (HSEET)
Ramakrishnan Krishnan¹,  Rajaraman Ramanarayanan²,  Vijaykrishnan Narayanan¹,  Yuan Xie¹,  Mary Jane Irwin^1
1Pennsylvania State University, ²Intel Corporation

Chair: Paul Tong
Co-Chair: Bao Liu

1:30PM
5B.1
Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM)
Yiran Chen,  Xiaobin Wang,  Hai Li,  Hongyue Liu,  Dimitar Dimitrov
Seagate LLC

2:00PM
5B.2
Investigating the Design, Performance, and Reliability of Multi-Walled Carbon Nanotube Interconnect
Arthur Nieuwoudt and Yehia Massoud
Rice University

2:30PM
5B.3
Micropipeline-Based Asynchronous Design Methodology for Robust System Design Using Nanoscale Crossbar
Rajat Subhra Chakraborty and Swarup Bhunia
Case Western Reserve University

2:50PM
5B.4
Statistical Evaluation of Split Gate Opportunities for Improved 8T/6T Column-decoupled SRAM Cell Yield
Rouwaida Kanj,  Rajiv Joshi,  Keunwoo Kim,  Richard Williams,  Sani Nassif
IBM

3:10PM
5B.5
High Resolution Read-out Circuit for DNA Label-Free Detection System
Daniela De Venuto
Politecnico di Bari, Italy

Chair: Kevin Brelsford
Co-Chair: Azadeh Davoodi

1:30PM
5C.1
Fast and Accurate Statistical Static Timing Analysis with Skewed Process Parameter Variation
Lin Xie and Azadeh Davoodi
University of Wisconsin at Madison

2:00PM
5C.2
Characterizing Intra-die Spatial Correlation Using Spectral Density Method
Qiang Fu,  Wai-Shing Luk,  Xuan Zeng
Fudan University, China

2:30PM
5C.3
Investigating the Impact of Fill Metal on Crosstalk-Induced Delay and Noise
Arthur Nieuwoudt¹,  Jamil Kawa²,  Yehia Massoud^1
1Rice University, ²Synopsys

2:50PM
5C.4
Process-Variation Statistical Modeling for VLSI Timing Analysis
Jui-Hsiang Liu¹,  Lumdo Chen²,  Charlie Chung-Ping Chen^1
1EE Department, National Taiwan University, Taiwan, ²UMC, Taiwan

3:10PM
5C.5
A Design Model for Random Process Variability
Victoria Wang¹,  Kanak Agarwal²,  Sani Nassif²,  Kevin Nowka²,  Dejan Markovic^1
1UCLA, ²IBM

Chair: Arthur Chojnacki
Co-Chair: Lech Jozwiak

1:30PM
5D.1
A Scratch-Pad Memory Aware Dynamic Loop Scheduling Algorithm
Ozcan Ozturk¹,  Mahmut Kandemir²,  Sri Hari Krishna Narayanan^2
1Marvell Semiconductors, ²Pennsylvania State University

2:00PM
5D.2
Amplifying Embedded System Efficiency via Automatic Instruction Fusion on a Post-Manufacturing Reconfigurable Architecture Platform
Allen C. Cheng
University of Pittsburgh

2:30PM
5D.3
Runtime Validation of Transactional Memory Systems
Kaiyu Chen¹,  Sharad Malik¹,  Priyadarsan Patra^2
1Princeton University, ²Intel Corporation

2:50PM
5D.4
SEU Vulnerability of Multiprocessor Systems and Task Scheduling for Heterogeneous Multiprocessor Systems
Makoto Sugihara
Toyohashi University of Technology

Chair: Xin Li
Co-Chair: Jose Silva Matos

3:45PM
6A.1
Node Criticality Computation for Circuit Timing Analysis and Optimization under NBTI Effect
Wenping Wang¹,  Shengqi Yang²,  Yu Cao^1
1Arizona State University, ²Intel Corporation

4:15PM
6A.2
Design for Reliability: A Novel Asynchronous Circuit Design with Fast Forwarding Technique at Advanced Technology Node
Chin-Khai Tang,  Chun-Yen Lin,  Yi-Chang Lu
Graduate Institute of Electronics Engineering, National Taiwan University

4:45PM
6A.3
Modeling of NBTI-Induced PMOS Degradation under Arbitrary Dynamic Temperature Variation
Bin Zhang and Michael Orshansky
University of Texas at Austin

5:05PM
6A.4
Reliability-Aware Optimization for DVS-Enabled Real-Time Embedded Systems
Foad Dabiri,  Navid Amini,  Mahsan Rofouei,  Majid Sarrafzadeh
University of California Los Angeles

5:25PM
6A.5
A Basis for Formal Robustness Checking
Goerschwin Fey and Rolf Drechsler
University of Bremen

Chair: Jay Sivagnaname
Co-Chair: Jianliang Li

3:45PM
6B.1
Quantified Impacts of Guardband Reduction on Design Process Outcomes
Kwangok Jeong,  Andrew B. Kahng,  Kambiz Samadi
University of California, San Diego

4:15PM
6B.2
Partitioning for Selective Flip-Flop Redundancy in Sequential Circuits
Uthman Alsaiari and Resve Saleh
The University of British Columbia

4:45PM
6B.3
A Root-Finding Method for Assessing SRAM Stability
Rouwaida Kanj,  Zhuo Li,  Rajiv Joshi,  Frank Liu,  Sani Nassif
IBM

5:05PM
6B.4
Cellwise OPC Based on Reduced Standard Cell Library
Hailong Jiao and Lan Chen
Department of Common Technology, Institute of Microelectronics, Chinese Academy of Sciences

5:25PM
6B.5
On-Chip Process Variation Detection and Compensation using Delay and Slew-Rate Monitoring Circuits
Amlan Ghosh¹,  Rahul Rao²,  Ching-te Chuang²,  Richard Brown^1
1University of Utah, Salt Lake City, UT 84112, ²IBM TJ Watson Research Center, Yorktown Heights, NY 10598

Chair: George Alexiou
Co-Chair: Yiran Chen

3:45PM
6C.1
Interval based X-masking for Scan Compression Architectures
Anshuman Chandra and Rohit Kapur
Synopsys, Inc.

4:15PM
6C.2
Two New Methods for Accurate Test Set Relaxation via Test Set Replacement
Stelios Neophytou and Maria Michael
University of Cyprus

4:45PM
6C.3
Embedded Deterministic Test Exploiting Care Bit Clustering and Seed Borrowing
Adam Kinsman and Nicola Nicolici
McMaster University

5:05PM
6C.4
A Built-In Test and Characterization Method for Circuit Marginality Related Failures
Alodeep Sanyal and Sandip Kundu
Univ. of Massachusetts

5:25PM
6C.5
On Chip Jitter Measurement through a High Accuracy TDC.
Akhil Garg and Prashant Dubey
STMicroelectronics Pvt Ltd

Chair: Vamsi Srikantam
Co-Chair: Sundareswaran Savithri

3:45PM
6D.1
Robust Analog Design for Automotive Aplications by Design Centering with Safe Operating Areas
Karl-Heinz Rooch¹,  Udo Sobe¹,  Andreas Ripp²,  Michael Pronath^2
1ZMD Zentrum Mikroelektronik Dresden AG, ²MunEDA GmbH

4:15PM
6D.2
Compact FinFET Memory Circuits with P-Type Data Access Transistors for Low Leakage and Robust Operation
Sherif Tawfik and Volkan Kursun
University of Wisconsin-Madison

4:45PM
6D.3
Towards Uniform Temperature Distribution in SOI Circuits Using Carbon Nanotube Based Thermal Interconnect
Yu Zhou,  Somnath Paul,  Swarup Bhunia
Case Western Reserve University

5:05PM
6D.4
Statistic Analysis of Power/Ground Networks Using Single-Node SOR Method
Zuying Luo¹ and Sheldon Xiang Dong Tan^2
1College of Information Science and Technology, Beijing Normal University， Beijing, 100875, ²Department of Electrical Engineering, University of California at Riverside, Riverside CA, 92521, USA

5:25PM
6D.5
IPOSA: A Novel Slack Distribution Algorithm for Interconnect Power Optimization
Xiang Qiu,  Yuchun Ma,  Xiangqing He,  Xianlong Hong
Tsinghua University