Plenary Session 2P

Wednesday March 19

8:30am-10:15am

 

Session Moderator:

Dr. Chi-Foon Chan

President& COO, Synopsys

 

Plenary Speech 2P.1

Wednesday, March 19

8:45am-9:15am

 

Consumerization of Electronics and Nanometer Technologies: Implications for Manufacturing Test

 

Sanjiv Taneja

Vice President, Encounter Test business unit

 Cadence Design Systems

 

Test has long been recognized as the bridge between Design and Manufacturing. However, innovation and deep integration in design and test tools has not kept pace with the consumerization of electronics and the rapidly evolving nanometer IC design and manufacturing. As a result, the full potential of Test has not been harnessed by the mainstream semiconductor community. The consumerization of electronics places significant new demands on low power, correctness and time-to-volume production. The rapid advances in nanometer technologies pose additional set of challenges due to the advanced physics effects and higher scales of transistor integration.

The EDA industry needs to establish a new paradigm and a "deep integration" to meet these challenges. During the design phase, a power-aware DFT architecture must integrate tightly with low power design and implementation flow. Later, during the manufacturing phase, the benefits of DFT must be seamlessly harnessed for rapid scan diagnostics based yield learning using not only logic information from the design database but also using layout timing and power information. This  keynote will discuss these challenges and possible solutions and scenarios.

 

About Sanjiv Taneja

Sanjiv Taneja is Vice President of the Encounter Test business unit at Cadence Design Systems. Under his leadership for the last two-and-a-half years, Cadenceís Test business has emerged in a stronger strategic, technological and product positions through a holistic strategy for manufacturing Test and deep, collaborative relationships with its customers and Test ecosystem partners.

 

Mr. Taneja started his career at Bell Labs in Murray Hill, NJ where he spent over 13 years in EDA software development and led the Custom/Analog Layout Automation group prior to the acquisition of Bell Labs Design Automation group by Cadence in 1998. Mr. Taneja holds a BS degree in Electrical Engineering from Indian Institute of Technology, New Delhi, a MS degree in Computer Science from Ohio State University, and MBA from New York University

 

 

 


Plenary Speech 2P.2

Wednesday, March 19

9:15am-9:45am

 

Statistical Techniques to Achieve Robustness and Quality 

 

 

Chandu Visweswariah

Research Staff Member

IBM Thomas J. Watson Research Center in Yorktown Heights, NY

 

Variability due to manufacturing, environmental and aging uncertainties constitutes one of the major challenges in continuing CMOS scaling.

Worst-case design is simply not feasible any more. This presentation will describe how statistical timing techniques can be used to reduce pessimism, achieve full-chip and full-process coverage, and enable robust design practices. A practical ASIC methodology based on statistical timing will be described. Robust optimization techniques will be discussed. Variability makes post-manufacturing testing a daunting task. Process coverage is a new metric that must be considered. Statistical techniques to improve quality in the context of at-speed test will be presented. Key research initiatives required to achieve elements of a statistical design flow will be described.

 

About Chandu Visweswariah

Chandu Visweswariah received a PhD in Computer Engineering from Carnegie Mellon University in 1989 and has been a Research Staff Member at the IBM Thomas J. Watson Research Center in Yorktown Heights, NY, ever since. He presently manages a circuit and interconnect analysis group. He has developed widely used circuit simulation, circuit optimization and statistical timing tools. He is the author or co-author of one book and 65 publications; he holds 14 U.S. patents with 25 more in the pipeline. In 2002, he was a visiting faculty member at the Eindhoven University of Technology. He was profiled in the EE Times "Great Minds, Great Ideas" 2005 project focusing on disruptive innovation. His team won the EDN "Innovation of the Year (EDA Tools Category)" and "Innovator of the Year" awards in 2006 for work on statistical timing. Two of Chandu's papers were selected for the "Best of ICCAD" compendium. Over the years, Chandu has won an IBM Corporate Award, two Outstanding Technical Achievement Awards, an Outstanding Innovation Award, a DAC Best Paper award, three IBM Supplemental Patent Issue Awards, two IBM Best Paper Awards, seven Research Division Awards and a Blue Chip Award. Chandu is a Fellow of the IEEE.

 

 


 

Plenary Speech 2P.3

Wednesday, March 19

9:45am-10:15am

 

The Greening of The SoC - How Electrical Engineers Will Save The World

 

 

Rich Goldman

Vice-President, Strategic Alliances for Synopsys and CEO of Synopsys Armenia, USA

 

Global Warming is hot! Climate change is occurring all around us, and the scientific evidence is increasingly overwhelming pointing to man's hand in the phenomena. We are already seeing huge impacts of Climate Change, much faster than anybody predicted, only a few short years ago. What can we do about? How can we slow and even reverse our impact on Climate Change? The key man made contributing factor is carbon emissions, primarily from coal fired power plants. We need to reduce the number of plants that we building, then the number of power plants that we require. The key to this is a reduction in power consumption. There are many everyday actions we can take individually to help.

 Al Gore states that Global Warming is an engineering problem that will be solved by engineers, addressing the issue as an opportunity, rather than additional cost. We will explore how engineers will impact Climate Change. Low Power IC design techniques will play a role in this just as new powerful techniques are coming into vogue.

 

About Rich Goldman

As vice president of Strategic Alliances for Synopsys, Rich is responsible for overseeing all interoperability programs and partnering programs with semiconductor vendors, IP providers, and platform vendors as well as the Synopsys worldwide university program. Rich also serves as CEO of Synopsys Armenia and is responsible for all aspects of the operation of Synopsys Armenia. Rich is a guest Professor at the Chinese Academy of Science, and is a Commissioner of the Advanced SOC Design Joint Lab Academic Committee there. He is also the Chairman of the Board of the Synopsys Outreach Foundation, a trustee of the State Engineering University of Armenia and a member of the Board of Directors of Silicon Valley Technical Institute.

 Prior to joining Synopsys fifteen years ago, Rich managed the ASIC library and design support software group while at Texas Instruments for 10 years. Rich started up TI ASICís Bangalore, India operation. Prior to TI, Rich worked at IBM, developing the digital simulator, AUSSIM. Rich has been active in standards organizations such as Accellera, EDIF, IEEE, Si2 and OVI for more than 20 years, including chairing the EDIF technical committee, and serving on the Board of Directors of Si2. Currently, Rich chairs the EDAC Interoperability and Quality Committee. Rich served as co-chair of the RAPID Board of Directors and was a member of the EIA/EDIF Steering Committee. Rich has a BSCS from Syracuse University and an MBA and MS Engineering Management from The University of Dallas. In 2007, Rich was conferred with an honorary doctorate degree from the State Engineering University of Armenia.

 

 


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