ISQED08

AdvanceProgram

 

ISQED 2008 CONFERENCE AT A GLANCE

Date

Time

TUTORIALS

Advanced Technology & Design Solutions in Design for Manufacturing Era

Room: Monterey/Carmel

Monday 3/17/08

9:00am-5:00pm

6:30pm-8:30pm

Evening Panel Discussion & Dinner

(Room: Donner)

Sponsored by Ponte Solutions

 

DFM: Is it Helping or Hurting?

Tuesday 3/18/08

8:30am-10:15am

PLENARY SESSION 1P

(Room: Donner)

Sponsored by Mentor Graphics

Keynote Speeches by:

 

Drew Gude, Microsoft, Robert Hum, Mentor Graphics

10:15am-10:30am

Morning Break

10:30am-12:00pm

Session 1A

Embedded Tutorial

SOC verification

Room: San Jose

Session 1B

Power Conscious Memories

Room: Santa Clara

Session 1C

Speed-up and Timing of Integrated Circuits

Room: Carmel

Session 1D

SER and noise tolerance

Room: Monterey

12:00pm-1:30pm

ISQED LUNCHEON

Sponsored by Synopsys

ISQED Quality Award (IQ Award 2008)

Sponsored by Microsoft

Best Paper Awards

Sponsored by Magma, and Synopsys

Committee Recognition Awards

(Room: Fir/Oak)

Luncheon Keynote

EDA Is Truly Where Electronics Quality Begins!

Antun Domic (Synopsys, USA)

 

1:30pm-3:30pm

Session 2A
Robust SRAM and analog circuits

Room: San Jose

Session 2B
Power and Thermal Management

Room: Santa Clara

Session 2C
Process Variations

Room: Monterey

Embedded

Sessions

E1

2E

EXHIBITS

Embedded

Tutorial 2D

3:30pm-3:45pm

Afternoon Break

   

3:45pm-5:45pm

Session 3A
System and Circuit Synthesis

Room: San Jose

Session 3B
Process, Characterization and Temperature-aware Design

Room: Santa Clara

Session 3C
Processor Test Verification / Delay Diagnosis

Room: Monterey

Embedded

Session

3E

Embedded Panel 3D

Wednesday 3/19/08

8:30am-10:15am

PLENARY SESSION 2P

(Room: Donner)

Keynote Speeches by:

 

Sanjiv Taneja, Cadence, Chandu Visweswariah, IBM, Rich Goldman, Synopsys

10:15am-10:30am

Morning Break

10:30am-12:00pm

Session 4A

Co-design Applications for IC Packages

Room: San Jose

Session 4B

Embedded Tutorial

Robust Design Methodologies

Room: Santa Clara

Session 4C

Tools and Interconnect

Room: Monterey

Session 4D

Sequential Analysis, Defect Modeling and At-speed Testing

Room: Carmel

12:00pm-1:30pm

Lunch and Panel Discussion LP2 

Sponsored by Cadence Design Systems

Statistical Design - Solutions Searching for Problems??

(Room: Donner/Siskiyou)

1:30pm-3:30pm

Session 5A

Modeling and analysis in physical design

Room: San Jose

Session 5B

Emerging Technologies and Novel Applications

Room: Santa Clara

Session 5C

Statistical timing

Room: Monterey

Session 5D

Modern Processor Design

Room: Carmel

3:30pm-3:45pm

 Afternoon Break

3:45pm-5:45pm

Session 6A

Modeling and Design of Reliable Circuits

Room: San Jose

Session 6B

Design for Manufacturing

Room: Santa Clara

Session 6C

Structural test

Room: Monterey

Session 6D

Advance Design Methodologies

Room: Carmel

                     

 


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