ISQED08 Embedded Tutorial 2D

Tuesday March 18, 2008

2:00pm-3:00pm

Siskiyou-Cascade-Sierra

How to Determine Best DFM Practices

Tom Jackson

Product Marketing Director, Encounter Test

Cadence Design Systems, Inc.

Summary: In this tutorial, there will be presentation of a methodology to ascertain the relative effectiveness of various DFM practices using results from volume diagnostics. Presently, rapid bring-up of semiconductor products is hampered by design and manufacturing interactions, commonly referred to as systematic defects. Moreover, today’s designs and process technology present those responsible for yield ramp with the challenge of determining the root cause of complex failures caused by voltage drop, signal cross-coupling and parasitic variations. A typical 45nm and beyond design flow will primarily consist of 3 stages – build, verify and correct. From a DFM standpoint, the build stage incorporates manufacturing know-how and limitations such that performance and yield entitlement can be achieved. However, even with such a “correct-by-construction” mindset it is necessary to verify and detect potential areas of yield or functionality concerns. These detected “hot spots” can then be used to correct and optimize the design. Present day complex and demanding designs may go through this flow iteratively until an acceptable level of DFM-cleanliness is achieved. Inspite of this design methodology, a product in silicon still demonstrates marginalities and consequently yield or performance issues due to undesirable design-process interactions. The tutorial will explain how correlating volume diagnostic results with DFM applications can be an effective and efficient means of locating such "problem areas" and can help provide a design-specific marching orders to manufacturing for mitigating systematic defects.     About Tom Jackson: Tom Jackson is currently product marketing director for the Cadence Encounter Test group and is responsible for DFT, ATPG and diagnostics products. Tom has over 20 years of EDA experience and began his career as a test engineer working on hardware accelerators. Tom has also held various positions in field applications and product marketing in the areas of design for test, formal verification, and yield management.   About Milind Weling:  Milind Weling is currently an Engineering Director at Cadence in the Sign-off and Silicon Optimization group. He leads manufacturing products and solutions that address present day design to silicon productization challenges. Previously, he was a Senior Manager at Sun Microsystems responsible for defining and driving leading edge process technology programs from 65 to 32nm.  Prior to Sun, Milind spent 14 years at VLSI Technology where he managed advanced process technology development and later at Philips Semiconductors' Computing & ASIC Business Line responsible for process and foundry interactions, and yield enhancement. He holds 44 patents and has authored over 70 technical papers mainly on technology integration, CMP and plasma etching.