Monday March 27, 2006
Emerging Technologies for VLSI Design
Anirudh Devgan, Magma Design Automation
Rajiv Joshi, Research Staff Member, IBM T J Watson Research Center, NY
Kaustav Banerjee, University of California, Santa Barbara, CA
Andre DeHon, California Institute of Technology, Pasadena, CA
This tutorial discusses emerging technologies for VLSI design. We will focus on three major components:
Computing with Nanowires Chemists can now construct wires which are a few atoms in diameter; these wires can be selectively field-effect gated, and wire crossings can act as programmable diodes. The tiny feature sizes offer a path to economically scale to atomic dimensions. However, the associated bottom-up synthesis techniques only produce highly regular structures and have high defect rates and minimal assembly control. In this tutorial, I review architectural techniques to bridge between lithographic and atomic-scale dimensions, build circuits from these nanowire building blocks, and tolerate defective and stochastic assembly.
Nanometer Technologies To continue scaling of the CMOS devices deep into sub-65nm technologies, fully depleted SOI, strained-Si on SiGe, FinFETs with double gate, and even further, three-dimensional circuits will be utilized to design high-performance circuits. We will discuss unique design aspects and issues resulting from this scaling such as gate-to-body tunneling, self-heating, reliability issues, and process variations. As the scaling approaches various physical limits, new design issues such as Vt modulation due to leakage, low-voltage impact ionization, and higher Vt,lin to maintain adequate Vt,sat, continue to surface. Circuit examples using SRAM are illustrated with the impact of technology. In case of FinFETs, impact of quantization and thermal impact on multi-finger devices is brought out. In this part of the tutorial, we will discuss these emerging trends and design issues related to aggressive device scaling.
Emerging Interconnect Technologies based on Carbon Nanotubes Carbon nanotube (CNT) interconnects have recently aroused a lot of interest as a promising candidate to meet the challenges faced by copper interconnects. This section of the tutorial will start with an overview of the key challenges in the domain of scaled copper interconnects and highlight their limitations arising due to a number of nanometer scale effects. Specifically, it will illustrate how combined effects of increasing copper resistivity, decreasing thermal conductivity of ILD materials and rising current densities in on-chip wires result in significant rise in interconnect temperatures that significantly degrades electromigration reliability and can limit their current carrying capacity in the near future. State-of-the-art CNT interconnects will be examined including their electrical, mechanical, and thermal properties as well as their fabrication issues. A comprehensive evaluation of CNT bundle interconnects vis-à-vis Cu will be presented and their impact on all aspects of VLSI circuits - performance, power dissipation and reliability - will be quantified, while accounting for practical limitations of the technology. Finally, hybridization of CNT and Cu interconnects will be discussed as a very attractive alternative for deep nanometer scale VLSI technologies.
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