ISQED05 Tutorials

Monday March 21, 2005

TUTORIALS

San Carlos/San Juan

 

TUTORIAL I

9:00am-12:00pm

 

Design of sub-90nm Circuits and Design Methodologies

 

Chair & Moderator:

Anirudh Devgan, IBM Research

 

Speakers:

Ruchir Puri, Research Staff Member, IBM TJ Watson Research Center, NY

Sachin Sapatnaker, Professor, Electrical & Computer Engineering, University of Minnesota

Tanay Karnik, Principal Engineer, Intel Circuit Research Labs, Hillsboro, OR

Rajiv Joshi, Research Staff Member, IBM T J Watson Research Center, NY

 

Summary:

This tutorial discusses design challenges of scaled CMOS circuits in sub-90nm technologies and the design methodologies required to design them in order to produce robust designs with desired power performance trade-off. We will focus on four major components:

Design challenges of sub-90nm CMOS circuits with particular emphasis on implications of each individual device scaling element on circuit design: To continue scaling of the CMOS devices deep into sub-90nm technologies, fully depleted SOI, strained-Si on SiGe, FinFETs with double gate, and even further, three-dimensional circuits will be utilized to design high-performance circuits. We will discuss unique design aspects and issues resulting from this scaling such as gate-to-body tunneling, self-heating, reliability issues, and process variations. As the scaling approaches various physical limits, new design issues such as Vt modulation due to leakage, low-voltage impact ionization, and higher Vtlin to maintain adequate Vtsat, continue to surface. In this part of tutorial, we will discuss these emerging trends and design issues related to aggressive device scaling.

 

Design methodologies for implementing robust circuits with desired power performance characteristics: With device dimensions approaching their physical limits, design methodologies are playing increasing significant role in achieving desired power and performance. In deep-submicron designs, chip performance is increasingly limited by the interconnect delay. Transistor delays decrease with technology scaling, while the narrower metal lines and space increase the relative delay associated with the interconnects.   As the designs are scaled to the next technology generation, the capacity of a same-sized die doubles, and the complexity and gate count of the design grows.  This results in devices and interconnects wires being placed in ever-increasing proximity. As a result, the cross-coupling capacitance between adjacent wires is increasing with each technology generation. All of these trends indicate that interconnect delays in sub-90nm technologies will continue to dominate the overall chip performance. The dominant interconnect delays require accurate net length and delay prediction during timing optimization to improve circuit performance. Not only does the design of circuits in sub-90nm technologies require a high-performance logic synthesis system but it also necessitates seamless integration of placement and synthesis design environments. In addition, with the coupling-capacitance issues generating increasing difficulties for design closure, more accurate wire routes must be known while optimizing the design in order to fix these problems earlier in the design cycle. This requires close integration of interconnect routing environment with placement and synthesis environments. In this part of tutorial, we will present the details of a high-performance synthesis system and a design flow in which placement, synthesis, and routing environments closely and seamlessly interact with each other to handle flat designs that are over 5 million gates with fast turn around design times in 90nm CMOS technology.

 

Managing leakage power: It is well known that with CMOS technologies beyond 90nm, leakage power is one of the most crucial design components which must be efficiently controlled in order to utilize the performance advantage from these technologies. We will focus on various techniques to analyze and control all components of leakage power placing particular emphasis on sub-threshold and gate leakage power. In addition, this part of tutorial will discuss low voltage circuit design under high intrinsic leakage, leakage monitoring and control techniques, effective transistor stacking, multi-threshold CMOS, dynamic threshold CMOS, well biasing techniques, and design of low leakage data-paths and caches.

 

Circuit Design in the Presence of Uncertainty: Nanometer design technologies must work under tight operating margins, and are therefore highly susceptible to any process and environmental variabilities.  This part of the tutorial will consider several factors related to reliability and yield.  With regard to environmental variations, it is important to build circuits that have well-distributed thermal properties, and to carefully design supply networks to provide reliable Vdd and ground levels throughout the chip.  On the process variation front, the effects of uncertainties in process variables must be modeled using statistical techniques, and they must be utilized to determine variations in the performance parameters of a circuit.  Instead of pessimistically treating timing in a worst-case manner as is conventionally done in static timing analysis, statistical techniques will have to be employed that directly predict the percentage of circuits that are likely to meet a timing specification.

 


 

TUTORIAL II

1:00pm-5:00pm

 

Modeling and Design of Chip-Package Interface

 

Chair & Moderator:

Anirudh Devgan, IBM Research

 

Speakers:

Luca Daniel, Massachusetts Institute of Technology, Cambridge, MA

Byron Krauter, IBM Microelectronics, Austin, TX

Lei He, UCLA EE Dept, Los Angeles, CA

 

 

Summary:

Signal integrity (SI) and power integrity are forecasted to be paramount issues for future chip and package designs. Larger number of IOs, higher frequencies, and tighter noise margins necessitate the merging of the design paradigms for chip IO and package. In this tutorial, we will shed light on a new chip-package co-design paradigm and all the technologies necessary to enable it. We will first discuss parameterized reduced order models accounting for all high frequency SI effects in the package that can be reliably and automatically extracted by field solvers. We will then introduce package-aware chip IO planning and placement, which is the key to chip-packaging co-design. Finally, we will cover detailed power and signal integrity modeling and optimization in package.  

 

 

 

 

 

 

 


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