ISQED05 Final Program

CONFERENCE AT A GLANCE

Date

Time

TUTORIALS

Design of sub-90nm CMOS Circuits and Design Methodologies

Package-Chip Co-Design Strategies & Challenges

Room: San Carlos/San Juan

Monday 3/21/05

9:00am-5:00pm

6:30pm-8:30pm

Evening Panel Discussion EP1

IP Creation and Use

What roadblocks are ahead or it is just clear and bumpy road?

Tuesday 3/22/05

8:30am-10:15am

PLENARY SESSION 1P

Keynote Speeches by:

John Kibarian,  Ashok K. Sinha,  Janusz Rajski

10:15am-10:30am

Morning Break

10:30am-12:00pm

Session 1A
 Tools and Flows for Quality Design

Room: San Carlos

Session 1B
High Level Power/Noise Reduction Techniques

Room: San Juan

Session 1C
Leakage and Dynamic Power Issues

Room: San Martin

Session 1D
Poster

City Foyer

 

 

 

 

 

12:00pm-1:00pm

ISQED LUNCHEON (Sponsored by Synopsys)

Committee Recognition Awards

Best Paper Awards (Sponsored by Synopsys & Magma Design Automation)

IP Quality: A Design, not a Verification Problem

Michael Keating

1:00pm-3:05pm

Session 2A
Test Application and Cost Reduction

Room: San Carlos

Session 2B
DFM and Physical Layout

 

Room: San Juan

Session 2C
Performance and Reliability Analysis for Yield Optimization

Room: San Martin

3:05pm-3:15pm

Afternoon Break

3:15pm-5:15pm

Session 3A
 Functional Verification and Test Generation

Room: San Carlos

Session 3B
Power Delivery and Distribution

 

Room: San Juan

Session 3C
Quality System Level Design and Synthesis

Room: San Martin

5:15pm-6:50pm

Session 4A
 DFM for Circuit Design

Room: San Carlos

Session 4B
Leakage and Reliability Management

Room: San Juan

Session 4C
Analog Test and BIST

Room: San Martin

7:00pm-9:00pm

Evening Panel Discussion EP2

Breakthroughs and Barriers in Nanoelectronics - Can we build systems with nano devices?

Wednesday 3/23/05

8:30am-10:15am

PLENARY SESSION 2P

Keynote Speeches by:

David Courtright, Kurt A. Wolf, Bernard Candaele

10:15am-10:30am

Morning Break

10:30am-12:00pm

SESSION 5A
Design Methods and Tools in DSM

 

Room: San Carlos

SESSION 5B
Design Techniques for Leakage Reduction

Room: San Juan

SESSION 5C
Variability Issues in Nanoscale Circuits

 

Room: San Martin

12:00pm-1:00pm

LUNCH BREAK

1:00pm-3:05pm

SESSION 6A
Issues in Noise and Timing

Room: San Carlos

SESSION 6B
Design Approaches for System in Package (SiP)

Room: San Juan

SESSION 6C
DSM Interconnect Issues

 

Room: San Martin

3:05pm-3:30pm

 Afternoon Break

3:30pm-5:35pm

SESSION 7A
Advances in Floor Planning

 

Room: San Carlos

SESSION 7B
Issues in On-Chip Communication and Analog/RF Designs

Room: San Juan

SESSION 7C
Robust Design under Parameter Variations

Room: San Martin

               

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