ISQED05 Plenary Session 2P
Wednesday March 23, 2005
8:30am - 10:15am
Valley Technical Institute
Eindhoven University of Technology, The Netherlands
Introduction & Announcements
Collaboration, Quality and Value in the Design Chain
Vice President and Chief Technology Officer, Cadence Design Systems
Meeting the challenges of product
development cycles and managing the complexity of increased
semiconductor functionality has created a demand for a virtual
reaggregation of the silicon design chain.
These challenges continue to multiply with the concurrent move to
This presentation, will address the
challenges by calling for an industry commitment to collaborate across
the design chain. It is
shown how collaboration is necessary for companies to meet
time-to-market demands and manage the increasing complexity in chip
design, while preserving the intellectual property of each member of the
design chain. The speaker will also discuss the need for developing
higher quality EDA tools as a means to the end of developing the next
generation of electronics products.
IP Quality: A New Model that Faces Methodology and Management
Kurt A. Wolf
Library Management Division
The promised value and productivity from
re-aggregating the IC design chain isn’t always delivered, in part
because of isolated IP product development/quality related practices,
and in part because of an inability, from a design management
perspective, to see “big picture” issues in the IP marketplace.
However, these challenges are not insurmountable.
The concern over IP quality has
rightfully grown over the past years as the future growth of the IC
industry depends on two factors; a) achieving higher levels of design
productivity and b) shifting internal resources towards creating and
delivering value-added user benefits that stimulate increased
end-product consumption. While
the second factor is not discussed in this presentation, there’s a
presumption that higher IP quality and productivity enables a shift of
resources to more applications-oriented design.
A pre-requisite to achieving the
productivity gains is substantial improvements in the level of IP
quality, coupled with increased forethought during product development.
This presentation describes a methodology to evaluate IP for SOC
integration. The focus is on
development & quality verification practices that also account for
the issues of IP integration.
the long-term growth of the semiconductor industry may be limited by the
lack of value placed on collaboration, support, quality verification,
and due diligence between SOC design teams and their IP partners.
This presentation also describes
improvements in the Hard IP business relationship between these groups
that enable dramatic growth through slight changes in communications
By developing reasonable expectations and
focusing on open discussion between each group, perspective begins to
shift. The true value of the
design team and IP partnership is a function of successful
collaborations – not when the user squeezes the last drop out of NRE,
royalty, per-use, or other financing models.
And the value-add of the partnership is realized when that
collaboration includes additional real, shared incentives that more
fully value the IP industry, rather than focus on purely lowest cost.
SoC Engineering Trends as Impacted by New Applications and System
Department Head, SoC, IC & EDA
Thales, Paris Colombes, France
increasing integration scale as well as the system and customer
requirements are important factors for a complete revisit of the
development models for electronic products. New customer models ask for
software driven electronics. Software engineering is moving to a
component-based and MDA development approach to be applied to embedded
applications. Hardware engineering is moving to SSDI System Level
Development and Reuse methodologies. The 2 approaches have now to be
further developed and combined for next generations SoC’s to get high
quality and adaptable designs at a reasonable development cost.
New application-level quality standards have also to be part of
the complete development flow.
demonstrated through several examples these new methodologies: system
engineering methodology on software radios (UML, PIM Platform
Independent Model and PSM Platform Specific Model) and its current
extension to the hardware parts (SCA, OCP potential extensions), system
engineering in line with the Common Criteria development and
qualification process for new security products (PP Protection Profile
and ST Security Target,…), development and validation methodology in
line with DO254 standard for new safety products in avionics (formal
verifications, …). Impacts on SoC architectures and design techniques
will be discussed during the talk.
International Society for
Quality Electronic Design (ISQED Org.)