Session 2B

1:00pm - 3:05pm

Design for Manufacturability and Quality

Co-Chairs

Sharad Saxena, PDF Solutions

Jay Michlin, Consultant

1:00pm

Introduction

1:05pm

2B-1    Design and Use of Memory-Specific Test Structures to Ensure SRAM Yield and Manufacturability, F. Duan, R. Castagnetti, R. Venkatraman, O. Kobozeva, S. Ramesh, LSI Logic Corp., Milpitas, CA    

1:35pm

2B-2            Advanced Physical Models for Mask Data Verification and Impacts on Physical Layout Synthesis, Qi-De Qian, Sheldon Tan1, IC Scope Research, Santa Clara, CA, 1University of California, Riverside, CA  

2:05pm

2B-3    New DFM Approach Abstracts AltPSM Lithography Requirements for Sub-100nm IC Design Domains, Pradiptya Ghosh, Chung-shin Kang, Michael Sanie, David   Pinto, Numerical Technologies, San Jose, CA  

2:35pm

2B-4            Methods and Framework for QA of Process Design Kits, Matthew Scott, Michael Peralta, J.D. Carothers1,             Paul Koch, Texas Instruments, Tucson, AZ,  1University of Arizona, Tucson, AZ     

2:50pm

2B-5    The iFlow Design Factory: Evolving Chip Design from an Art to a Process, through Adaptive Resource Management, and Qualified Data Exchange, Gilles-Eric Descamps, Satish Bagalkotkar, Subramanian Ganesan, Sridhar Subramaniam, Hem Hingarh, Silicon Access Networks, San Jose, CA