Session EP1

Sponsored by EE Times

Evening Panel Discussion

6:30pm- 8:30pm

Are the interoperability standards for EDA too little / too late for real SOC designs?  

Organizer: Pallab Chatterjee, President, SiliconMap, LLC

Moderator: Richard Goering, Managing Editor Design Automation, EETimes

Description

The panel will examine the emerging interoperability standards and contrast them to the time to market requirements for current designs. There are supporting statements for interoperability standards. However, there are concerns about the results and the delayed delivery. The proposed interoperability standards may not address features of the process technology at the time standards are adopted . A second issue facing the design community is the impact on the product specific design methodologies used and the cost in time/money to shift to new methodologies required for these tools that may be more homogenized than optimized for particular types of SOC. Additional issues include support issues for the flow for the standards vs custom flows, point tools vs sub-flow tools, data reuse and migration vs new data creation for use in the current tools, and tool directions and roadblocks for advanced (sub 0.10um) DSM processes. The panel is comprised of EDA, Foundry, Semiconductor Manufacturers, and Design Centers who will discuss their experiences with in-house developed flows, multi-vendor flows based on multiple APIs and the time-to-market tradeoffs of these solutions as an alternative to the 2-3 year delay waiting for committee based standards.

Panelists

Noel Strader, Technical Marketing, Avanti Corporation

Joe Hutt, Vice President Technical Sales, Magma Design Automation

Andrew Moore, Design Service Marketing, EDA, TSMC, North America

Sunil Joshi, Vice President, Design Automation and Compute Resources, Sun

Greg Spirakis, VP Intel Architecture Group, Director Design Tehnology, Intel

Steve Ferguson, COO and Director of Engineering, SiliconMap