Plenary Session I

8:30am-11:50am

Co-Chairs:

Kris Verma, ISQED Plenary Chair

Res Saleh, ISQED Conference Chair

8:30am

Welcome and Introduction

8:45am

1P.1 IP REUSE QUALITY:  “Intellectual Property” or “Intense Pain?”

John Chilton

Sr. VP and General Manager , Synopsys, Inc.  

As systems on a chip become more complex, reuse of third-party intellectual property (IP) becomes more necessary to meet time-to-market deadlines.  However, issues surrounding IP quality are very much unresolved.  Poor IP quality is the key reason why many IP users feel that “IP” is actually an acronym for “Intense Pain.” . There are major inconsistencies surrounding basic quality, including fully synchronous design, registered inputs and outputs for IP blocks, and completion of full specifications before design. All these inconsistencies contribute to difficulties in using the IP and integrating it into a chip design. One of the key reasons why quality is still such an issue within the IP community is the issue of “reuse” versus “salvaging.”  Much of the IP sold over the last few years wasn’t really designed for reuse.  Instead, it was designed for use in a single chip, then later repackaged (i.e., salvaged) as IP. There has also been tremendous interest in creating IP repositories--fancy Java-based, Web-accessed, and multi-featured custom products meant to hold the wealth of IP.  Along the way, though, we forgot to create enough fully reusable IP to warrant these repository investments. Although the challenges in the IP business may seem daunting (and there are many more besides just those that concern quality), they are well worth the effort when you consider the rewards. There’s a tremendous need for IP to address the growing productivity gap, which represents a great opportunity for the third-party IP industry.  

9:25am

1P.2 Why Integrated Yield Management is a Necessity

Y. David Lepejian

President, CEO and Chairman of the Board, HPL

Improving semiconductor yield is a multi-facetted process that must include design, manufacturing, and test.  An integrated approach enables companies to rapidly reach higher levels of revenue and profitability. Incorporating design-for-yield concepts early, improving the quality of the test programs, and applying new technology to accelerate the measurement and correction of failure sources in the production process combine to have powerful effect upon company profits, product quality, and time to volume.

10:05am

Break

10:30am

1P.3 Design Success: Foundry Perspective   

Jim Kupec

President UMC USA

Leading edge foundries are rolling out new process technologies every two years with today's advance processes capable of producing a quarter billion transistor on a thumb-nail sized chip. The growth of the fabless business model has enabled many companies to organize and build value with the strength of their design capabilities. Quality is often reflected by the continued success of design practices resulting in market success. The many styles of design implementations provided by a large number of companies sharing a common process helps provide a Darwinian view of quality practices. The interaction with design flows, libraries, special purpose IP, memory types are important considerations. This talk will address the trade-offs and successful design technologies used in foundries.  

11:10am

1P.4 What you don’t know CAN hurt you: Designing for survival in a sub-wavelength environment

Y.C. (Buno) Pati

President and CEO, Numerical Technologies   

The semiconductor industry’s promise to deliver an endless array of chip designs to match the voracious appetite for smaller, faster, cheaper devices is in danger of ringing hollow.  We could make this commitment with confidence up to recently.  But, lately we’ve hit the wall.  We’re crashing through the sub-wavelength barrier and we’re feeling our way toward designing and manufacturing chips in a challenging new environment without benefit of some key process technologies.   Now, to survive and thrive, chipmakers are turning to phase shifting—just a novel, clever concept a few short years ago—as a critical and necessary enabler of producing integrated circuits at dimensions of 0.13 micron and below.  Inevitably, chip designers are following suit, not just to match the chipmakers in their march to smaller feature sizes, but to polish their own competitive edge with high-performance chip designs that are easy to produce.  They’re breaking out of a somewhat isolated mold, knowing that shrinking design times and increasing layout complexity call for new tools and expertise.  Most acknowledge that the success of their designs, and indeed, their future viability depends on quickly adopting the tools and expertise that their chip making customers are using so effectively.