3:25pm

Introduction

3:30pm

2C.1 Design for Testability in Nanometer Technologies:

Searching for Quality (Invited)

T.W. Williams, and Rohit Kapur, Synopsys, Mountain View, CA

3:55pm

2C.2 Low Power Testing of VLSI Circuits: Problems and Solutions (Invited)

Patrick Girard, LIRMM, Montpellier, France

4:20pm

2C.3 On Effective IDDQ Testing of Low Voltage CMOS Circuits Using Leakage Control Techniques

Zhanping Chen, Liqiong Wei and Kaushik Roy, Purdue University, IN

4:45pm

2C.4 Efficient Hierarchical Approach to Test Generation for

Digital Systems

Raimund Ubar, and Jaan Raik, Tallinn Technical University, Tallinn, ESTONIA

5:10pm

2C.5 Quality of Electronic Design: from Architectural Level

to Test Coverage

O.P. Dias*, J. Semião**, M.B. Santos***, I.M.Teixeira***, and J.P. Teixeira***, *Escola Superior de Tecnologia Instituto Politécnico de Setúbal, INESC, Portugal, **Escola Superior de Tecnologia Universidade do Algarve, INESC, Portugal, ***Instituto Superior Técnico Universidade Técnica de Lisboa, INESC, Portugal